74VCX16838 Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
July 1997
Revised June 2005
74VCX16838
Low Voltage 16-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16838 contains sixteen non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 16-bit word wide mode. All
outputs can be placed into 3-State through use of the OE
Pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74VCX16838 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX16838 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
Compatible with PC100 and PC133 DIMM module
specifications
s
1.65V–3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
(CLK to O
n
)
3.0 ns max for 3.0V to 3.6V V
CC
4.0 ns max for 2.3V to 2.7V V
CC
8.0 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
r
24 mA @ 3.0V V
CC
r
18 mA @ 2.3V V
CC
r
6 mA @ 1.65V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Ideal for SDRAM DIMM modules
s
Latch-up performance exceeds 300 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74VCX16838MTD
Package Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
I
0
–I
15
O
0
–O
15
CLK
REGE
Description
Output Enable Input (Active LOW)
Inputs
Outputs
Clock Input
Register Enable Input
© 2005 Fairchild Semiconductor Corporation
DS500034
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74VCX16838
Connection Diagram
Truth Table
Inputs
CLK
REGE
H
H
L
L
X
I
n
H
L
H
L
X
OE
L
L
L
L
H
Outputs
O
n
H
L
H
L
Z
n
n
X
X
X
H Logic HIGH
L Logic LOW
X Don’t Care, but not floating
Z High Impedance
n
LOW-to-HIGH Clock Transition
Functional Description
The 74VCX16838 consists of sixteen selectable non-invert-
ing buffers or registers with word wide modes. Mode func-
tionality is selected through operation of the CLK and
REGE pin as shown by the truth table. When REGE is held
at a logic HIGH the device operates as a 16-bit register.
Data is transferred from I
n
to O
n
on the rising edge of the
CLK input. When the REGE pin is held at a logic LOW the
device operates in a flow through mode and data propa-
gates directly from the I to the O outputs. All outputs can be
3-STATE by holding the OE pin at a logic HIGH.
Logic Diagram
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2
74VCX16838
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
)
Outputs 3-STATE
Outputs Active (Note 3)
DC Input Diode Current (I
IK
) V
I
0V
DC Output Diode Current (I
OK
)
V
O
0V
V
O
!
V
CC
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
0.5V to
4.6V
0.5V to
4.6V
0.5V to
4.6V
0.5V to V
CC
0.5V
50 mA
50 mA
50 mA
r
50 mA
r
100 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 4)
Power Supply
Operating
Data Retention Only
Input Voltage
Output Voltage (V
O
)
Output in Active States
Output in “OFF” State
Output Current in I
OH
/I
OL
V
CC
V
CC
V
CC
3.0V to 3.6V
2.3V to 2.7V
1.65V to 2.3V
0V to V
CC
0V to 3.6V
1.65V to 3.6V
1.2V to 3.6V
0.3V to
3.6V
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
t/
'
V)
V
IN
0.8V to 2.0V, V
CC
3.0V
r
24 mA
r
18 mA
r
6 mA
40
q
C to
85
q
C
10 ns/V
Note 2:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics (2.7V
V
CC
d
3.6V)
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
V
OL
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
I
OFF
I
CC
Input Leakage Current
3-STATE Output Leakage
Power-OFF Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
Conditions
V
CC
(V)
2.7–3.6
2.7–3.6
Min
2.0
0.8
V
CC
0.2
2.2
2.4
2.2
0.2
0.4
0.4
0.55
V
V
Max
Units
V
V
100
P
A
12 mA
18 mA
24 mA
100
P
A
12 mA
18 mA
24 mA
2.7–3.6
2.7
3.0
3.0
2.7–3.6
2.7
3.0
3.0
2.7–3.6
2.7–3.6
0
2.7–3.6
2.7–3.6
0V
d
V
I
d
3.6V
0V
d
V
O
d
3.6V
V
I
V
IH
or V
IL
0V
d
(V
I
, V
O
)
d
3.6V
V
I
V
CC
or GND
V
CC
d
(V
I
, V
O
)
d
3.6V (Note 5)
V
IH
V
CC
0.6V
r
5.0
r
10
10
20
P
A
P
A
P
A
P
A
P
A
r
20
750
'
I
CC
Note 5:
Outputs disabled or 3-STATE only.
3
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74VCX16838
DC Electrical Characteristics (2.3V
d
V
CC
d
2.7V)
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
V
OL
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
I
I
OZ
I
OFF
I
CC
Input Leakage Current
3-STATE Output Leakage
Power-OFF Leakage Current
Quiescent Supply Current
Conditions
V
CC
(V)
2.3–2.7
2.3–2.7
Min
1.6
0.7
V
CC
0.2
2.0
1.8
1.7
0.2
0.4
0.6
V
V
Max
Units
V
V
100
P
A
6 mA
12 mA
18 mA
100
P
A
12 mA
18 mA
2.3–2.7
2.3
2.3
2.3
2.3–2.7
2.3
2.3
2.3–2.7
2.3–2.7
0
2.3–2.7
V0
d
V
I
d
3.6V
0V
d
V
O
d
3.6V
V
I
V
I
V
IH
or V
IL
V
CC
or GND
0V
d
(V
I
, V
O
)
d
3.6V
V
CC
d
(V
I
, V
O
)
d
3.6V (Note 6)
r
5.0
r
10
10
20
P
A
P
A
P
A
P
A
r
20
Note 6:
Outputs disabled or 3-STATE only.
DC Electrical Characteristics (1.65V
d
V
CC
2.3V)
Symbol
V
IH
V
IL
V
OH
V
OL
I
I
I
OZ
I
OFF
I
CC
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Input Leakage Current
3-STATE Output Leakage
Power-OFF Leakage Current
Quiescent Supply Current
I
OH
I
OH
I
OL
I
OL
Conditions
V
CC
(V)
1.65 - 2.3
1.65 - 2.3
Min
0.65
u
V
CC
0.35
u
V
CC
V
CC
0.2
1.25
0.2
0.3
Max
Units
V
V
V
V
100
P
A
6 mA
100
P
A
6 mA
1.65 - 2.3
1.65
1.65 - 2.3
1.65
1.65 - 2.3
1.65 - 2.3
0
1.65 - 2.3
0V
d
V
I
d
3.6V
0V
d
V
O
d
3.6V
V
I
V
I
V
IH
or V
IL
V
CC
or GND
0V
d
(V
I
, V
O
)
d
3.6V
V
CC
d
(V
I
, V
O
)
d
3.6V (Note 7)
r
5.0
r
10
10
20
P
A
P
A
P
A
P
A
r
20
Note 7:
Outputs disabled or 3-STATE only.
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4
74VCX16838
AC Electrical Characteristics
(Note 8)
T
A
Symbol
Parameter
V
CC
Min
f
MAX
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
S
t
H
t
W
t
OSHL
t
OSLH
Maximum Clock Frequency
Propagation Delay I
n
to O
n
(REGE 0)
Propagation Delay CLK to O
n
(REGE 1)
Propagation Delay REGE to O
n
Output Enable Time
Output Disable Time
Setup Time
Hold Time
Pulse Width
Output to Output Skew
(Note 9)
250
0.8
0.8
0.8
0.8
0.8
1.0
0.7
1.5
0.5
2.5
3.0
3.0
3.5
3.5
40
q
C to
85
q
C, C
L
V
CC
Min
200
1.0
1.0
1.0
1.0
1.0
1.0
0.7
1.5
30 pF, R
L
500
:
V
CC
Min
100
1.8V
r
0.15V
Max
MHz
7.0
8.0
8.0
9.4
7.0
ns
ns
ns
ns
ns
ns
ns
ns
0.75
ns
Units
3.3V
r
0.3V
Max
2.5V
r
0.2V
Max
3.5
4.0
4.0
4.7
3.9
1.5
1.5
1.5
1.5
1.5
2.5
1.0
4.0
0.5
Note 8:
For C
L
50
P
F, add approximately 300 ps to the AC maximum specification.
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Extended AC Electrical Characteristics
(Note 10)
T
A
Symbol
Parameter
Min
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
S
t
H
Propagation Delay I
n
to O
n
(REGE
Propagation Delay REGE to O
n
Output Enable Time
Output Disable Time
Setup Time
Hold Time
0)
1)
1.0
1.4
1.0
1.0
1.0
1.0
0.7
Propagation Delay CLK to O
n
(REGE
0
q
C to
85
q
C, R
L
C
L
500
:
V
CC
50 pF
3.3V
r
0.3V
Units
Max
2.8
3.3
3.3
3.8
3.8
ns
ns
ns
ns
ns
ns
ns
Note 10:
This parameter is guaranteed by characterization but not tested.
Dynamic Switching Characteristics
Symbol
V
OLP
Parameter
Quiet Output Dynamic Peak V
OL
C
L
30 pF, V
IH
Conditions
V
CC
, V
IL
0V
V
CC
(V)
1.8
2.5
3.3
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
30 pF, V
IH
V
CC
, V
IL
0V
1.8
2.5
3.3
V
OHV
Quiet Output Dynamic Valley V
OH
C
L
30 pF, V
IH
V
CC
, V
IL
0V
1.8
2.5
3.3
T
A
25
q
C
0.25
0.6
0.8
Typical
Units
V
0.25
0.6
0.8
1.5
1.9
2.2
V
V
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
V
CC
V
I
V
I
V
CC
Conditions
1.8V, 2.5V or 3.3V, V
I
0V or V
CC
, V
CC
0V or V
CC
, f
10 MHz,
0V or V
CC
T
A
25
q
C
6
7
20
Typical
Units
pF
pF
pF
1.8V, 2.5V or 3.3V
1.8V, 2.5V or 3.3V
5
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