HSP50110
Digital Quadrature Tuner
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DATASHEET
FN3651
Rev 6.00
March 2001
The Digital Quadrature Tuner (DQT) provides many of the
functions required for digital demodulation. These functions
include carrier LO generation and mixing, baseband
sampling, programmable bandwidth filtering, baseband AGC,
and IF AGC error detection. Serial control inputs are provided
which can be used to interface with external symbol and
carrier tracking loops. These elements make the DQT ideal
for demodulator applications with multiple operational modes
or data rates. The DQT may be used with HSP50210 Digital
Costas Loop to function as a demodulator for BPSK, QPSK,
8-PSK OQPSK, FSK, FM, and AM signals.
The DQT processes a real or complex input digitized at rates
up to 52 MSPS. The channel of interest is shifted to DC by a
complex multiplication with the internal LO. The quadrature
LO is generated by a numerically controlled oscillator (NCO)
with a tuning resolution of 0.012Hz at a 52MHz sample rate.
The output of the complex multiplier is gain corrected and fed
into identical low pass FIR filters. Each filter is comprised of a
decimating low pass filter followed by an optional
compensation filter. The decimating low pass filter is a 3 stage
Cascaded-Integrator-Comb (CIC) filter. The CIC filter can be
configured as an integrate and dump filter or a third order CIC
filter with a (sin(X)/X)
3
response. Compensation filters are
provided to flatten the (sin(X)/X)
N
response of the CIC. If none
of the filtering options are desired, they may be bypassed.
The filter bandwidth is set by the decimation rate of the CIC
filter. The decimation rate may be fixed or adjusted
dynamically by a symbol tracking loop to synchronize the
output samples to symbol boundaries. The decimation rate
may range from 1-4096. An internal AGC loop is provided to
maintain the output magnitude at a desired level. Also, an
input level detector can be used to supply error signal for an
external IF AGC loop closed around the A/D.
The DQT output is provided in either serial or parallel formats
to support interfacing with a variety DSP processors or digital
filter components. This device is configurable over a general
purpose 8-bit parallel bidirectional microprocessor control bus.
Features
• Input Sample Rates to 52MSPS
• Internal AGC Loop for Output Level Stability
• Parallel or Serial Output Data Formats
• 10-Bit Real or Complex Inputs
• Bidirectional 8-Bit Microprocessor Interface
• Frequency Selectivity <0.013Hz
• Low Pass Filter Configurable as Three Stage Cascaded-
Integrator-Comb (CIC), Integrate and Dump, or Bypass
• Fixed Decimation from 1-4096, or Adjusted by NCO
Synchronization with Baseband Waveforms
• Input Level Detection for External IF AGC Loop
• Designed to Operate with HSP50210 Digital Costas Loop
• 84 Lead PLCC
Applications
• Satellite Receivers and Modems
• Complex Upconversion/Modulation
• Tuner for Digital Demodulators
• Digital PLLs
• Related Products: HSP50210 Digital Costas Loop;
A/D Products HI5703, HI5746, HI5766
• HSP50110/210EVAL Digital Demod Evaluation Board
Ordering Information
PART NUMBER
HSP50110JC-52
HSP50110JI-52
TEMP.
RANGE (
o
C)
0 to 70
-40 to 85
PACKAGE
84 Ld PLCC
84 Ld PLCC
PKG. NO.
N84.1.15
N84.1.15
Block Diagram
COMPLEX
MULTIPLIER
10
90
o
0
o
NCO
LOW PASS FIR
FILTER
GCA
LEVEL
DETECT
8
PROGRAMMABLE
CONTROL
INTERFACE
DUMP
RE-SAMPLING
NCO
10
CARRIER
TRACKING CONTROL
Q DATA
SAMPLE STROBE
SAMPLE RATE
CONTROL
LOOP
FILTER
LOW PASS FIR
FILTER
LEVEL
DETECT
10
I DATA
GCA
REAL OR COMPLEX
INPUT DATA
10
IF AGC
CONTROL
CONTROL/STATUS
BUS
FN3651 Rev 6.00
March 2001
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HSP50110
Pinout
HSP50110 (PLCC)
TOP VIEW
IIN6
IIN7
IIN8
IIN9
HI/LO
SSTRB
SPH4
V
CC
SPH3
SPH2
SPH1
SPH0
LOTP
OEI
IOUT9
IOUT8
IOUT7
GND
IOUT6
IOUT5
IOUT4
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
IIN5
IIN4
IIN3
IIN2
GND
IIN1
IIN0
ENI
QIN9
QIN8
QIN7
QIN6
QIN5
QIN4
V
CC
QIN3
QIN2
QIN1
QIN0
PH1
PH0
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
CFLD
WR
RD
A2
GND
A1
A0
C7
C6
C5
C4
C3
C2
V
CC
C1
C0
COF
COFSYNC
SOF
SOFSYNC
GND
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
IOUT3
IOUT2
IOUT1
IOUT0
DATARDY
V
CC
CLK
GND
QOUT9
QOUT8
QOUT7
QOUT6
QOUT5
GND
QOUT4
QOUT3
QOUT2
QOUT1
QOUT0
OEQ
V
CC
Pin Descriptions
NAME
V
CC
GND
IIN9-0
QIN9-0
ENI
TYPE
-
-
I
I
I
+5V Power Supply.
Ground.
In-Phase Input. Data input for in-phase (real) samples. Format may be either two’s complement or offset binary format
(see I/O Formatting/Control Register in Table 9). IIN9 is the MSB.
Quadrature Input. Data input for quadrature (imaginary) samples. Format may be either two’s complement or offset bi-
nary format (see I/O Formatting/Control Register in Table 9). QIN9 is the MSB.
Input Enable. When ENI is active ‘low’, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the rising
edge of CLK. This input also controls the internal data processing as described in the Input Controller Section of the
data sheet. ENI is active ‘low’.
Carrier Phase Offset. The phase of the internally generated carrier frequency may be shifted by 0, 90, 180, or 270 de-
grees by controlling these pins (see Synthesizer/Mixer Section). The phase mapping for these inputs is given in Table 1.
Carrier Frequency Load. This input loads the Carrier Frequency Register in the Synthesizer NCO (see
Synthesizer/Mixer Section). When this input is sampled ‘high’ by clock, the contents of the Microprocessor Interface
Holding Registers are transferred to the carrier frequency register in the Synthesizer NCO (see Microprocessor Inter-
face Section).
NOTE: This pin must be ‘low’ when loading other configuration data via the Microprocessor In-
terface. Active high Input.
Carrier Offset Frequency Input. This serial input is used to load the Carrier Offset Frequency into the Synthesizer NCO
(see Serial Interface Section). The new offset frequency is shifted in MSB first by CLK starting with the clock cycle after
the assertion of COFSYNC.
Carrier Offset Frequency Sync. This signal is asserted one CLK cycle before the MSB of the offset frequency data word
(see Serial Interface Section).
DESCRIPTION
PH1-0
CFLD
I
I
COF
I
COFSYNC
I
FN3651 Rev 6.00
March 2001
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HSP50110
Pin Descriptions
NAME
SOF
TYPE
I
(Continued)
DESCRIPTION
Sampler Offset Frequency. This serial input is used to load the Sampler Offset Frequency into the Re-Sampler NCO
(see Serial Interface Section). The new offset frequency is shifted in MSB first by CLK starting with the clock cycle after
assertion of SOFSYNC.
Sampler Offset Frequency Sync. This signal is asserted one CLK cycle before the MSB of Sampler Offset Frequency
data word (see Serial Interface Section).
Address Bus. These inputs specify a target register within the Microprocessor Interface (see Table 5). A2 is the MSB.
This input is setup and held to the rising edge of WR.
Control Bus. This is the bidirectional data bus for reads and writes to the Microprocessor Interface (see Microprocessor
Interface Section). C7 is the MSB.
Write. This is the write strobe for the Microprocessor Interface (see Microprocessor Interface Section).
Read. This is the read enable for the Microprocessor Interface (see Microprocessor Interface Section).
In-Phase Output. The data on these pins is output synchronous to CLK. New data on IOUT9-0 is indicated by the as-
sertion of the DATARDY pin. Data may be output parallel or serial mode (see Output Formatter Section). In the parallel
mode, IOUT9 is the MSB. When the serial mode is used, IOUT0 is data, and IOUT9 is the serial clock. Other pins not
used in serial mode may be set high or low via the control interface.
Quadrature Output. The data on these pins is output synchronous to CLK. New data on the QOUT(9-0) pins is indicated
by the DATARDY pin. Data may be output parallel or serial mode. In the parallel mode, IOUT9 is the MSB. When the
serial mode is used, QOUT0 is data.
Data Ready. This output is asserted on the first clock cycle that new data is available on the IOUT and QOUT data
busses (see Output Formatter Section). This pin may be active ‘high’ or ‘low’ depending on the configuration of the I/O
Formatting/Control Register (see Table 9). In serial mode, DATARDY is asserted one IQ clock before for first bit of serial
data.
In-Phase Output Enable. This pin is the three-state control for IOUT9-0. When OEI is ‘high’, the IOUT bus is held in the
high impedance state.
Quadrature Output Enable. This pin is the three-state control for QOUT9-0. When OEQ is ‘high’, the QOUT bus is held
in the high impedance state.
Local Oscillator Test Point. This output is the MSB of the Synthesizer NCO phase accumulator (see Synthesizer/Mixer
Section). This is provided as a test point for monitoring the frequency of the Synthesizer NCO.
Sample Strobe. This is the bit rate strobe for the bit rate NCO. SSTRB has two modes of operation: continuous update
and sampled. In continuous update mode, this is the carry output of the Re-Sampler NCO. In sampled mode, SSTRB
is active synchronous to the DATARDY signal for parallel output mode. The sampled mode is provided to signal the
nearest output sample aligned with or following the symbol boundary. This signal can be used with SPH(4-0) below to
control a resampling filter to time shift its impulse response to align with the symbol boundaries.
Sample Phase. These are five of the most significant 8 bits of the Re-Sampler NCO phase accumulator. Which five bits
of the eight is selected via the Chip Configuration Register (see Table 11). These pins update continuously when the
SSTRB output is in the continuous update mode. When the SSTRB pin is in the sampled mode, SPH4-0 update only
when the SSTRB pin is asserted. In the sampled mode, these pins indicate how far the bit phase has advanced past
the symbol boundary when the output sample updates. SPH4 is the MSB.
HI/LO. The output of the Input Level Detector is provided on this pin (see Input Level Detector Section). The sense of
the HI/LO pin is set via the Chip Configuration Register (see Table 11). This signal can be externally averaged and used
to control the gain of an amplifier to close an AGC loop around the A/D converter. This type of AGC sets the level based
on the median value on the input.
Clock. All I/O’s with the exception of the output enables and the microprocessor interface are synchronous to clock.
SOFSYNC
A2-0
C7-0
WR
RD
IOUT9-0
I
I
I/0
I
I
O
QOUT9-0
O
DATARDY
O
OEI
OEQ
LOTP
SSTRB
I
I
0
0
SPH4-0
0
HI/LO
0
CLK
I
FN3651 Rev 6.00
March 2001
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HSP50110
UPPER LIMIT
†
LOWER LIMIT
†
HI/LO OUTPUT SENSE
†
LOOP
FILTER
AGC
LOW PASS FILTERING
12
COMPLEX
MULTIPLIER
11
LOOP GAIN
†
AGC THRESHOLD
†
HI/LO
LEVEL
DETECT
THRESHOLD FOR
EXTERNAL AGC
†
SYNTHESIZER/MIXER
INPUT
CONTROLLER
LEVEL
DETECT
OEI
10
F
O
R
M
A
T
IIN0-9
CLK
QIN0-9
ENI
10
IOUT0-9
DATARDY
QOUT0-9
OEQ
10
12
11
10
INPUT MODE
†
INPUT FORMAT
†
PH0-1
CFLD
COF
COFSYNC
COF EN
†
WORD WIDTH
†
SOF
SOFSYNC
A0-2
WR
RD
C0-7
SHIFT REG
COS
10
SIN
10
32
DECIMATING
FILTER
COMPENSATION
FILTER
SYNTHESIZER
NCO
8
CENTER
FREQUENCY
†
PHASE
OFFSET
†
LOTP
CLK
DIVIDER
RE-SAMPLER
NCO
5
32
SAMPLER CENTER
FREQUENCY
†
SSTRB
SPH0-4
SHIFT REG
RE-SAMPLER
MICROPROCESSOR INTERFACE
SOF EN
†
WORD WIDTH
†
†
Indicates data downloaded via microprocessor interface
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF HSP50110
Functional Description
The Digital Quadrature Tuner (DQT) provides many of the
functions needed for digital demodulation including: carrier LO
generation, mixing, low-pass filtering, baseband sampling,
baseband AGC, and IF AGC error detection. A block diagram
of the DQT is provided in Figure 1. The DQT processes a real
or complex input at rates up to 52 MSPS. The digitized IF is
input to the Synthesizer/Mixer where it is multiplied by a
quadrature LO of user programmable frequency. This
operation tunes the channel of interest to DC where it is
extracted by the Low Pass FIR Filtering section. The filter
bandwidth is set through a user programmable decimation
factor. The decimation factor is set by the Re-Sampler which
controls the baseband sampling rate. The baseband sample
rate can be adjusted by an external symbol tracking loop via a
serial interface. Similarly, a serial interface is provided which
allows the frequency of the Synthesizer/Mixer’s NCO to be
controlled by an external carrier tracking loop. The serial
interfaces were designed to mate with the output of loop filters
on the HSP50210 Digital Costas Loop.
The DQT provides an input level detector and an internal AGC
to help maintain the input and output signal magnitudes at user
specified levels. The input level detector compares the input
signal magnitude to a programmable level and generates an
error signal. The error signal can be externally averaged to set
the gain of an amplifier in front of the A/D which closes the
AGC loop. The output signal level is maintained by an internal
AGC loop closed around the Low Pass Filtering. The AGC loop
gain and gain limits are programmable.
Input Controller
The input controller sets the input sample rate of the
processing elements. The controller has two operational
modes which include a Gated Input Mode for processing
sample rates slower than CLK, and an Interpolated Input Mode
for increasing the effective time resolution of the samples. The
mode is selected by setting bit 1 of the I/O Formatting Control
Register in Table 9.
In Gated Input Mode, the Input Enable (ENI) controls the data
flow into the input pipeline and the processing of the internal
elements. When this input is sampled “low” by CLK, the data
on IIN0-9 and QIN0-9 is clocked into the processing pipeline;
when ENI is sampled “high”, the data inputs are disabled. The
Input Enable is pipelined to the internal processing elements
so that they are enabled once for each time ENI is sampled
low. This mode minimizes the processing pipeline latency, and
the latency of the part’s serial interfaces while conserving
power.
Note: the effective input sample rate to the internal
FN3651 Rev 6.00
March 2001
Page 4 of 25
HSP50110
processing elements is equal to the frequency with which
ENI is asserted “low”.
In Interpolated Input Mode, the ENI input is used to insert
zeroes between the input data samples. This process
increases the input sample rate to the processing elements
which improves the time resolution of the processing chain.
When ENI is sampled “high” by CLK, a zero is input into the
processing pipeline. When ENI is sampled “low” the input data
is fed into the pipeline.
Note: Due to the nature of the rate
change operation, consideration must be given to the
scaling and interpolation filtering required for a particular
rate change factor.
In either the Gated or Interpolated Input Mode, the Synthesizer
NCO is gated by the ENI input. This only allows clocking of the
NCO when external samples are input to the processing
pipeline. As a result, the NCO frequency must be set relative to
the input sample rate, not the CLK rate (see Synthesizer/Mixer
Section).
NOTE: Only fixed interpolation rates should be
used when operating the part in Interpolated Mode at the
Input Controller.
The Level Detector responds to such an input by
producing a square wave output with a 50% duty cycle for
a wide range of thresholds. This square wave integrates to
zero, indicating no error for a range of input signal
amplitudes.
Synthesizer/Mixer
The Synthesizer/Mixer spectrally shifts the input signal of
interest to DC for subsequent baseband filtering. This function
is performed by using a complex multiplier to multiply the input
with the output of a quadrature numerically controlled oscillator
(NCO). The multiplier operation is:
I
OUT
= I
IN
x cos (
c
) - Q
IN
x sin (
c
)
Q
OUT
= I
IN
x sin (
c
) + Q
IN
x cos (
c
)
(EQ. 3)
(EQ. 4)
The complex multiplier output is rounded to 12 bits. For real
inputs this operation is similar to that performed by a
quadrature downconverter. For complex inputs, the
Synthesizer/Mixer functions as a single-sideband or image
reject mixer which shifts the frequency of the complex samples
without generating images.
TO COMPLEX MULTIPLIER
COS
10
SIN
10
REG
REG
SIN/COS
ROM
R
E
G
REG
REG
+
COF
ENABLE
†
MUX
32
COF
REG
0
32
CF
REG
PHASE
ACCUMULATOR
MUX
2
11
+
8 R PHASE OFFSET
†
E
G
0
LOAD
†
Input Level Detector
The Input Level Detector generates a one-bit error signal for an
external IF AGC filter and amp. The error signal is generated
by comparing the magnitude of the input samples to a user
programmable threshold. The HI/LO pin is then driven “high” or
“low” depending the relationship of its magnitude to the
threshold. The sense of the HI/LO pin is programmable so that
a magnitude exceeding the threshold can either be
represented as a “high” or “low” logic state. The threshold and
the sense of the HI/LO pin are configured by loading the
appropriate control registers via the Microprocessor Interface
(see Tables 7 and 11).
The high/low outputs can be integrated by an external loop
filter to close an AGC loop. Using this method the gain of the
loop forces the median magnitude of the input samples to the
threshold. When the magnitude of half the samples are above
the threshold and half are below, the error signal is integrated
to zero by the loop filter.
The algorithm for determining the magnitude of the complex
input is given by:
Mag(I,Q) = | I | + .375 x | Q | if | I | > | Q |
or:
Mag(I,Q) = | Q | + .375 x |I| if | Q | > | I | ,
(EQ. 2)
(EQ. 1)
CFLD
†
Controlled via
microprocessor interface.
PH0-1
LOTP
COFSYNC
COF
R
E
G
SYNC
SHIFT REG
SYNC
CARRIER
FREQUENCY
†
LOAD CARRIER
FREQUENCY
†
Using this algorithm, the magnitude of complex inputs can be
estimated with an error of <0.55dB or approximately 6.5%. For
real inputs, the magnitude detector reduces to a an absolute
value detector with negligible error.
Note: an external AGC loop using the Input Level Detector
may go unstable for a real sine wave input whose
frequency is exactly one quarter of the sample rate (F
S
/4).
FIGURE 2. SYNTHESIZER NCO
The quadrature outputs of the NCO are generated by driving a
sine/cosine lookup table with the output of a phase
accumulator as shown in Figure 2. Each time the phase
accumulator is clocked, its sum is incremented by the sum of
the contents of the Carrier Frequency (CF) Register and the
Carrier Offset Frequency (COF) Register. As the accumulator
sum transitions from 0 to 2
32
, the SIN/COS ROM produces
FN3651 Rev 6.00
March 2001
Page 5 of 25
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