HI7188
TM
Data Sheet
December 2000
File Number
4016.5
8-Channel, 16-Bit, High Precision, Sigma-
Delta A/D Sub-System
The HI7188 is an easy-to-use 8-Channel sigma-delta
programmable A/D
subsystem
ideal for low frequency
physical and electrical measurements in scientific, medical,
and industrial applications. The subsystem has complete on-
chip capabilities to support moving the intelligence from the
system controller and towards the sensors. This gives the
designer faster and more flexible configurability without the
traditional drawbacks of low throughput per channel, higher
power or cost per channel. Extreme design complexity and
excessive software overhead is eliminated.
The HI7188 contains a fully differential 8 channel multiplexer,
Programmable Gain Instrumentation Amplifier (PGIA), 4th
order sigma-delta ADC, integrating filter, line noise rejection
filters, calibration and data RAMs, clock oscillator, and a
microsequencer. Communication with the HI7188 is
performed via the serial I/O port, and is compatible with most
synchronous transfer formats, including both the
Motorola/Intersil 6805/11 series SPI, QSPI and Intel 8051
series SSR protocols.
The powerful on-board microsequencer provides automatic
conversions on the multiplexed input channels (up to 8) by
controlling all channel switching, filtering and calibration. The
microsequencer supports on-the-fly multiplexer
reconfiguration, forty to fifty times faster throughput than the
competition and zero step response delay during internal or
external multiplexer channel changes. A simple set of
commands gives the user control over calibration, PGIA
gain, and bipolar/unipolar modes on a per channel basis.
Number of channels to convert, data coding, line noise
rejection, etc. is programmed at the chip level. The
calibration RAMs allow the user to read and write system
calibration data while the data RAMs provide a read support
of the conversion results for each channel.
This design is effectively eight 16-bit (for 96dB noise-free
dynamic range) Sigma-Delta A/D converters combined with
a microsequencer and an eight-channel multiplexer in a
single package. The HI7188 provides 120dB line-noise
rejection at 240 samples/second/channel (in 60Hz line-
rejection mode) and 200 samples/second/channel (in 50Hz
line-rejection mode) base output data rates. By reusing
multiplexer channels for the same input, throughput can
Fully Differential 8-Channel Multiplexer and Reference
Features
• Fully Differential 8-Channel Multiplexer and Reference
• Automatic Channel Switching with Zero Latency
• 240 Conversions Per Second Per Channel
• 16-Bit Resolution with No Missing Codes
• 0.0015% Integral Non-Linearity
• Fully Software Configurable
- 120dB Rejection of 60/50Hz Line Noise
- Channel Conversion Order and Number of Active
Channels
- True Bipolar or Unipolar Input Range Per Channel
- PGIA Gain Per Channel
- 2-Wire or 3-Wire Interface
• Chopper Stabilized PGIA with Gains of 1 to 8
• Serial Data I/O Interface, SPI Compatible
• 3 Point System Calibration
• Low Power Dissipation of 30mW (Typ)
Applications
• Multi-Channel Industrial Process Controls
• Weight Scales
• Medical Patient Monitoring
• Laboratory Instrumentation
• Gas Monitoring System
• Reference Literature
- AN9504 “A Brief Introduction to Sigma Delta
Conversion”
- TB329 “Intersil Sigma-Delta Calibration Techniques”
- AN9518 “Using the HI7188 Evaluation Kit”
- AN9610 “Interfacing the HI7188 to a Microcontroller”
- AN9538 “Using the HI7188 Serial Interface
Ordering Information
PART
NUMBER
HI7188IN
HI7188EVAL
TEMP.
RANGE (
o
C)
-40 to 85
25
PACKAGE
44 Ld MQFP
Evaluation Kit
PKG. NO.
Q44.10x10
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright © Intersil Corporation 2000
HI7188
Pin Descriptions
44 LEAD
MQFP
41
42
43
44
1
PIN NAME
MODE
SCLK
SDO
SDIO
OSC
1
PIN DESCRIPTION
Mode input. Used to select between Synchronous Self Clocking (MODE = 1) or Synchronous External Clocking
(MODE = 0) for the Serial Port.
Serial interface clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the falling
edge.
Serial Data Out. Serial data is read from this line when using a 3-wire serial protocol such as the Motorola Serial
Peripheral Interface.
Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial
Interface using a 2-wire serial protocol.
Oscillator clock input for the device. A crystal connected between OSC
1
and OSC
2
will provide a clock to the
device, or an external oscillator can drive OSC
1
. The oscillator frequency should be 3.6864MHz to maintain Line
Noise Rejection.
Used to connect a crystal source between OSC
1
and OSC
2
. Leave open otherwise.
Positive Digital supply (+5V).
Digital supply ground.
Negative analog power supply (-5V).
Analog input low for Channel 1.
Analog input high for Channel 1.
Analog input low for Channel 2.
Analog input high for Channel 2.
Analog input low for Channel 3.
Analog input high for Channel 3.
Analog input low for Channel 4.
Analog input high for Channel 4.
Analog input low for Channel 5.
Analog input high for Channel 5.
Analog input low for Channel 6.
Analog input high for Channel 6.
Analog input low for Channel 7.
Analog input high for Channel 7.
Analog input low for Channel 8.
Analog input high for Channel 8.
Common mode voltage. Must be tied to the mid point of AV
DD
and AV
SS
.
External reference input. Should be negative referenced to V
RHI
.
External reference input. Should be positive referenced to V
RLO
.
Positive analog power supply (+5V).
Active low Reset pin. Used to initialize modulator, filter, RAMs, registers and state machines.
Calibration active output. Indicates that at least one active channel is in a calibration mode.
Multiplexer control output. Indicates that the conversion for the active channel is complete.
Logical channel count output (LSB).
Logical channel count output.
Logical channel count output (MSB).
End of scan output. Signals the end of a channel scan (all active channels have been converted) and data is
available to be read. Remains low until data RAM is read.
I/O reset (active low) input. Resets serial interface state machine only.
Active low chip select pin. Used to select a serial data transfer cycle. When high the SDO and SDIO pins are
three-state.
2
3, 30
4, 29, 39
5, 6, 27, 28
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
31
32
33
34
35
36
37
38
40
OSC
2
DV
DD
DGND
AV
SS
V
INL1
V
INH1
V
INL2
V
INH2
V
INL3
V
INH3
V
INL4
V
INH4
V
INL5
V
INH5
V
INL6
V
INH6
V
INL7
V
INH7
V
INL8
V
INH8
V
CM
V
RLO
V
RHI
AV
DD
RST
CA
MXC
A
0
A
1
A
2
EOS
RSTI/O
CS
5
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