CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
AV
EE
, DV
EE
= -4.94V to -5.46V, V
CC
= +4.75 to +5.25V, V
REF
= Internal,
T
A
= +25°C
HI5741BI
T
A
= -40°C TO +85°C
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
(Note 5)
Differential Linearity Error, DNL
Offset Error, I
OS
Full Scale Gain Error, FSE
Full Scale Gain Drift
Offset Drift Coefficient
Full Scale Output Current, I
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Throughput Rate
Output Voltage Settling Time
(
1
/
16
th Scale Step Across Segment)
Singlet Glitch Area, GE (Peak)
Output Slew Rate
Output Rise Time
Output Fall Time
Spurious Free Dynamic Range within a Window
(Note 4)
(Note 4)
(Note 4)
TEST CONDITIONS
MIN
14
TYP
-
±1.0
-
±0.5
8
3.2
±150
-
-20.48
-
-
11
20
1
1,000
675
470
87
77
75
80
78
79
MAX
-
1.5
1.75
1.0
75
10
-
0.05
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
Bits
LSB
LSB
LSB
A
%
ppm
FSR/°C
A/°C
mA
V
MSPS
ns
ns
pV•s
V/s
ps
ps
dBc
dBc
dBc
dBc
dBc
dBc
“Best Fit Straight Line”, T
A
= +25°C
“Best Fit Straight Line”, T
A
= -40°C to +85°C
(Note 5) T
A
= +25°C
(Note 5)
(Notes 3, 5)
With Internal Reference
(Note 4)
-1.5
-1.75
-1.0
-
-
-
-
-
-1.25
100
-
-
-
-
-
-
-
-
-
-
-
-
R
L
= 64(Note 4) - Settling to 0.024%
R
L
= 64(Note 4) - Settling to 0.012%
R
L
= 64(Note 4)
R
L
= 64DAC Operating in Latched Mode (Note 4)
R
L
= 64DAC Operating in Latched Mode (Note 4)
R
L
= 64DAC Operating in Latched Mode (Note 4)
f
CLK
= 10 MSPS, f
OUT
= 1.23MHz, 2MHz Span
f
CLK
= 20 MSPS, f
OUT
= 5.055MHz, 2MHz Span
f
CLK
= 40 MSPS, f
OUT
= 16MHz, 10MHz Span
f
CLK
= 50 MSPS, f
OUT
= 10.1MHz, 2MHz Span
f
CLK
= 80 MSPS, f
OUT
= 5.1MHz, 2MHz Span
f
CLK
= 100 MSPS, f
OUT
= 10.1MHz, 2MHz Span
FN4071 Rev 12.00
September 20, 2006
Page 3 of 13
HI5741
Electrical Specifications
AV
EE
, DV
EE
= -4.94V to -5.46V, V
CC
= +4.75 to +5.25V, V
REF
= Internal,
T
A
= +25°C
(Continued)
HI5741BI
T
A
= -40°C TO +85°C
PARAMETER
Spurious Free Dynamic Range to Nyquist
(Note 4)
TEST CONDITIONS
f
CLK
= 10 MSPS, f
OUT
= 1.023MHz, 5MHz Span
f
CLK
= 10 MSPS, f
OUT
= 2.02MHz, 5MHz Span
f
CLK
= 25 MSPS, f
OUT
= 2.02MHz, 12.5MHz Span
f
CLK
= 50 MSPS, f
OUT
= 5.055MHz, 25MHz Span
f
CLK
= 75 MSPS, f
OUT
= 7.52MHz, 37.5MHz Span
f
CLK
= 100 MSPS, f
OUT
= 10.1MHz, 50MHz Span
Multi-Tone Power Ratio
(MTPR)
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, V
REF
Internal Reference Voltage Drift
Internal Reference Output Current Sink/Source
Capability
Internal Reference Load Regulation
Amplifier Input Impedance
Amplifier Large Signal Bandwidth
Amplifier Small Signal Bandwidth
Reference Input Impedance (CTL IN)
Reference Input Multiplying Bandwidth (CTL IN)
DIGITAL INPUTS
(D9-D0, CLK, INVERT)
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic Current, I
IH
Input Logic Current, I
IL
Digital Input Capacitance, C
IN
TIMING CHARACTERISTICS
Data Setup Time, t
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
PD
CLK Pulse Width, t
PW1
, t
PW2
POWER SUPPLY CHARACTERISTICS
IV
EEA
IV
EED
IV
CCD
Power Dissipation
Power Supply Rejection Ratio
NOTES:
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Gain Error measured as the error in the ratio between the full scale output current and the current through R
SET
(typically 1.28mA). Ideally the
ratio should be 16.
4. Parameter guaranteed by design or characterization and not production tested.
5. All devices are 100% tested at +25°C.
6. Dynamic Range must be limited to a 1V swing within the compliance range.
7. In testing MTPR, tone frequencies ranged from 1.95MHz to 3.05MHz. The ratio is measured as the range from peak power to peak distortion in
the region of removed tones.
(Note 5)
(Note 5)
(Note 5)
(Note 5)
V
CC
5%,
V
EE
5%
-
-
-
-
-
42
75
13
650
5
50
95
20
-
-
mA
mA
mA
mW
A/V
See Figure 1 (Note 4)
See Figure 1 (Note 4)
See Figure 1 (Note 4)
See Figure 1 (Note 4)
3
0.5
-
1.0
2.0
0.25
4.5
0.85
-
-
-
-
ns
ns
ns
ns
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 4)
2.0
-
-
-
-
-
-
-
-
3.0
-
0.8
400
700
-
V
V
A
A
pF
(Note 5)
(Note 4)
(Note 4)
I
REF
= 0 to I
REF
= -500A
(Note 4)
4.0V
P-P
Sine Wave Input, to Slew Rate Limited (Note 4)
1.0V
P-P
Sine Wave Input, to -3dB Loss (Note 4)
(Note 4)
R
L
= 50, 100mV Sine Wave, to -3dB Loss at I
OUT
(Note 4)
-1.27
-
-500
-
-
-
-
-
-
-1.23
50
-
100
3
1
5
12
75
-1.17
-
+50
-
-
-
-
-
-
V
V/°C
A
V
M
MHz
MHz
k
MHz
8 Tones, no Clipping, 110kHz Spacing, 220kHz spacing
between tones 4 and 5, f
CLK
= 20 MSPS (Note 7)
MIN
-
-
-
-
-
-
-
TYP
86
85
77
74
73
71
76
MAX
-
-
-
-
-
-
-
UNITS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
FN4071 Rev 12.00
September 20, 2006
Page 4 of 13
HI5741
Timing Diagrams
50%
CLK
D13-D0
ERROR BAND
V
GLITCH AREA =
1
/
2
(H x W)
I
OUT
HEIGHT (H)
t
PD
t
SETT
WIDTH (W)
t(ps)
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
t
PW1
t
PW2
CLK
t
SU
t
HLD
D13-D0
t
SU
t
HLD
t
SU
t
HLD
50%
t
PD
t
SETT
I
OUT
t
PD
t
SETT
t
PD
t
SETT
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
工业自动化与控制
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
