DATASHEET
HI3338
8-Bit, CMOS R2R D/A Converter
The HI3338 family are CMOS high speed R2R voltage
output digital-to-analog converters. They can operate from a
single +5V supply, at video speeds, and can produce
“rail-to-rail” output swings. Internal level shifters and a pin for
an optional second supply provide for an output range below
digital ground.
The data complement control allows the inversion of input
data while the latch enable control provides either
feedthrough or latched operation. Both ends of the R2R
ladder network are available externally and may be
modulated for gain or offset adjustments. In addition, “glitch”
energy has been kept very low by segmenting and
thermometer encoding of the upper 3 bits.
The HI3338 is manufactured to give low dynamic power
dissipation, low output capacitance, and inherent latch-up
resistance.
FN4134
Rev.3.00
July 2004
Features
• CMOS Low Power (Typ) . . . . . . . . . . . . . . . . . . . .100mW
• R2R Output, Segmented for Low “Glitch”
• CMOS/TTL Compatible Inputs
• Fast Settling (Typ) . . . . . . . . . . . . . . . . . . 20ns to
1
/
2
LSB
• Feedthrough Latch for Clocked or Unclocked Use
• Accuracy(Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .
0.5
LSB
• Data Complement Control
• High Update Rate (Typ) . . . . . . . . . . . . . . . . . . . . . 50MHz
• Unipolar or Bipolar Operation
• Linearity (INL)
- HI3338KIB . . . . . . . . . . . . . . . . . . . . . . . . . .
0.75
LSB
• Pb-free Available
Ordering Information
PART NUMBER
HI3338KIB
HI3338KIBZ
(Note)
TEMP.
RANGE (°C)
-40 to 85
-40 to 85
PACKAGE
16 Ld SOIC
16 Ld SOIC
(Pb-free)
PKG.
DWG. #
M16.3
M16.3
Applications
• TV/Video Display
• High Speed Oscilloscope Display
• Digital Waveform Generator
• Direct Digital Frequency Synthesis
• Wireless Communication
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
HI3338 (SOIC)
TOP VIEW
D7
D6
D5
D4
D3
D2
D1
V
SS
1
2
3
4
5
6
7
8
16 V
DD
15 LE
14 COMP
13 V
REF
+
12 V
OUT
11 V
REF
-
10 V
EE
9 D0
FN4134 Rev.3.00
July 2004
Page 1 of 9
HI3338
Absolute Maximum Ratings
DC Supply-Voltage Range. . . . . . . . . . . . . . . . . . . . . . . -0.5V to +8V
(V
DD
- V
SS
or V
DD
- V
EE
, Whichever Is Greater)
Input Voltage Range
Digital Inputs (LE, COMP D0 - D7). . . . V
SS
- 0.5V to V
DD
+ 0.5V
Analog Pins (V
REF
+, V
REF
-, V
OUT
) . . . .V
DD
- 8V to V
DD
+ 0.5V
DC Input Current
Digital Inputs (LE, COMP, D0 - D7) . . . . . . . . . . . . . . . . . .
20mA
Recommended Supply Voltage Range . . . . . . . . . . . . . 4.5V to 7.5V
Thermal Information
Thermal Resistance (Typical)
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range, T
STG
. . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(Lead Tips Only)
Operating Conditions
HI3338KIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
ACCURACY
Resolution
Integral Linearity Error
Differential Linearity Error
Gain Error
Offset Error
DIGITAL INPUT TIMING
Update Rate
Update Rate
Set Up Time t
SU1
Set Up Time t
SU2
Hold Time t
H
Latch Pulse Width t
W
Latch Pulse Width t
W
OUTPUT PARAMETERS
Output Delay t
D1
Output Delay t
D2
Rise Time t
r
Settling Time t
S
Output Impedance
Glitch Area
Glitch Area
REFERENCE VOLTAGE
V
REF
+ Range
V
REF
- Range
V
REF
+ Input Current
T
A
= 25
o
C, V
DD
= 5V, V
REF
+ = 4.608V, V
SS
= V
EE
= V
REF
- = GND, LE clocked at 20MHz, R
L
1M,
Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
8
See Figure 4
See Figure 4
Input Code = FF
HEX
, See Figure 3
Input Code = 00
HEX
, See Figure 3
-
-
-
-
-
-
-
-
-
-
0.75
0.5
0.5
0.25
Bits
LSB
LSB
LSB
LSB
To Maintain
1
/
2
LSB Settling
V
REF
- = V
EE
= -2.5V, V
REF
+ = +2.5V
For Low Glitch
For Data Store
For Data Store
For Data Store
V
REF
- = V
EE
= -2.5V, V
REF
+ = +2.5V
R
L
Adjusted for 1V
P-P
Output
From LE Edge
From Data Changing
10% to 90% of Output
10% to Settling to
1
/
2
LSB
V
REF
+ = 6V, V
DD
= 6V
DC
DC
-
-
-
-
-
50
20
-2
8
5
5
25
-
-
-
-
-
-
-
MHz
MHz
ns
ns
ns
ns
ns
-
-
-
-
120
-
25
22
4
20
160
150
250
-
-
-
-
200
-
-
ns
ns
ns
ns
pV-s
pV-s
V
REF
- = V
EE
= -2.5V, V
REF
+ = +2.5V
-
(+) Full Scale (Note 1)
(-) Full Scale (Note 1)
V
REF
+ = 6V, V
DD
= 6V
V
REF
- + 3
V
EE
-
-
-
40
V
DD
V
REF
+ - 3
50
V
V
mA
FN4134 Rev.3.00
July 2004
Page 3 of 9
HI3338
Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
D7
D6
D5
D4
D3
D2
D1
V
SS
D0
V
EE
V
REF
-
V
OUT
Digital Ground
Least Significant Bit. Input Data Bit
Analog Ground
Reference Voltage Negative Input
Analog Output
DESCRIPTION
Most Significant Bit
Input
Data
Bits
(High = True)
Latch Operation
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is not
recommended for applications requiring low output “glitch”
energy: there is no guarantee of the simultaneous changing of
input data or the equal propagation delay of all bits through the
converter. Several parameters are given if the converter is to
be used in either of these modes: t
D2
gives the delay from the
input changing to the output changing (10%), while t
SU2
and t
H
give the set up and hold times (referred to LE rising edge)
needed to latch data. See Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use. Data
must meet the given t
SU1
set up time to the LE falling edge,
and the t
H
hold time from the LE rising edge. The delay to the
output changing, t
D1
, is now referred to the LE falling edge.
There is no need for a square wave LE clock; LE must only
meet the minimum t
W
pulse width for successful latch
operation. Generally, output timing (desired accuracy of
settling) sets the upper limit of usable clock frequency.
V
REF
+ Reference Voltage Positive Input
COMP
LE
V
DD
Data Complement Control input. Active High
Latch Enable Input. Active Low
Digital Power Supply, +5V
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus the
bottom “2R” resistor are returned to V
REF
- this is the (-) full-
scale reference. The “P” channel (pull up) transistor of each
driver is returned to V
REF
+, the (+) full-scale reference.
In unipolar operation, V
REF
- would typically be returned to
analog ground, but may be raised above ground (see
specifications). There is substantial code dependent current
that flows from V
REF
+ to V
REF
- (see V
REF
+ input current in
specifications), so V
REF
- should have a low impedance path to
ground.
In bipolar operation, V
REF
- would be returned to a negative
voltage (the maximum voltage rating to V
DD
must be
observed). V
EE
, which supplies the gate potential for the
output drivers, must be returned to a point at least as negative
as V
REF
-. Note that the maximum clocking speed decreases
when the bipolar mode is used.
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically 1.5V.
The 8 data bits, D0 (weighted 2
0
) through D7 (weighted 2
7
),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of V
DD
and V
SS
, are shifted to operate between V
DD
and V
EE
. V
EE
optionally at ground or at a negative voltage, will
be discussed under bipolar operation. All further logic elements
except the output drivers operate from the V
DD
and V
EE
supplies.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
Static Characteristics
The ideal 8-bit D/A would have an output equal to V
REF
- with
an input code of 00
HEX
(zero scale output), and an output
equal to 255/256 of V
REF
+ (referred to V
REF
-) with an input
code of FFHEX (full scale output). The difference between the
ideal and actual values of these two parameters are the
OFFSET and GAIN errors, respectively; see Figure 3.
If the code into an 8-bit D/A is changed by 1 count, the output
should change by 1/255 (full-scale output-zero scale output). A
deviation from this step size is a differential linearity error, see
Figure 4. Note that the error is expressed in fractions of the
FN4134 Rev.3.00
July 2004
Page 5 of 9
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