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8
1-88
HI1386
March 2003
8-Bit, 75 MSPS, Flash A/D Converter
Features
•
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•
•
•
•
•
•
•
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•
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Differential Linearity Error
±0.5
LSB or Less
Integral Linearity Error
±0.5
LSB or Less
Built-In Integral Linearity Compensation Circuit
High-Speed Operation with Maximum Conversion Rate
(Min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MSPS
Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . 17pF
Wide Analog Input Bandwidth (Min for Full Scale Input) 150MHz
Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.2V
Low Power Consumption (Typ) . . . . . . . . . . . . . . . . . . . . . 580mW
Low Error Rate
Operable at 50% Clock Duty Cycle
Capable of Driving 50Ω Loads
Direct Replacement for CXA1386
Video Digitizing
RGB Graphics Processing
HDTV (High Definition TV)
Radar Systems
Communication Systems
Direct RF Down-Conversion
Digital Oscilloscopes
Description
The HI1386 is an 8-bit, high-speed flash analog-to-digital
converter IC capable of digitizing analog signals at a maxi-
mum rate of 75 MSPS. The digital I/O levels of this A/D con-
verter are compatible with ECL 100K/10KH/10K.
The HI1386 is available in the commercial and industrial
temperature range and is supplied in 28 lead plastic DIP and
44 lead ceramic LCC packages.
Part Number Information
PART
NUMBER
HI1386JCP
HI1386AIL
TEMP.
RANGE (
o
C)
-20 to 75
-20 to 100
PACKAGE
28 Ld PDIP
44 Ld CLCC
PKG. NO.
E28.6A-S
J44.B
Applications
Pinouts
HI1386 (PDIP)
TOP VIEW
DGND2
DV
EE
HI1386 (CLCC)
TOP VIEW
AV
EE
AV
EE
AV
EE
39 NC
38 NC
37 AGND
36 V
IN
35 AGND
34 V
RM
33 AGND
32 V
IN
31 AGND
30 NC
29 NC
18 19 20 21 22 23 24 25 26 27 28
LINV
DV
EE
2
DGND 3
(LSB) D0 4
D1 5
D2 6
D3 7
D4 8
D5 9
D6 10
(MSB) D7 11
DGND 12
DV
EE
13
MINV 14
27 V
RT
26 AV
EE
25 AGND
24 V
IN
23 AGND
22 V
RM
21 AGND
20 V
IN
19 AGND
18 AV
EE
17 V
RB
16 CLK
15 CLK
NC 7
(LSB) D0 8
D1 9
D2 10
D3 11
D4 12
D5 13
D6 14
(MSB) D7 15
DGND2 16
NC 17
6
5
4
3
2
1 44 43 42 41 40
DV
EE
V
RB
V
RT
LINV 1
NC
NC
NC
28 AV
EE
DGND1
AV
EE
DGND1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
AV
EE
MINV
CLK
NC
NC
CLK
NC
FN3583.5
HI1386
Functional Block Diagram
MINV
R1
V
RT
R/2
R
1
R
D7 (MSB)
2
R
D6
COMPARATOR
63
R
V
IN
64
R
65
OUTPUT
D3
R
126
R
R2
V
RM
R
128
R
D0 (LSB)
129
127
ENCODE
LOGIC
D1
D2
D4
D5
R
191
R
V
IN
192
R
193
R
254
R
255
V
RB
CLK
CLK
R3
R/2
CLOCK
DRIVER
LINV
2
HI1386
Pin Descriptions
PIN NUMBER
DIP
19, 21,
23, 25
LCC
31, 33,
35, 37
SYMBOL
AGND
I/O
-
STANDARD
VOLTAGE
LEVEL
0V
EQUIVALENT CIRCUIT
DESCRIPTION
Analog GND. Used as GND for
input buffers and latches of
comparators. Isolated from DGND,
DGND1, and DGND2.
Analog V
EE
-5.2V (Typ). Internally
connected to DV
EE
(Resistance:
4Ω to 6Ω). Bypass with 0.1µF to
AGND.
CLK Input.
18, 26,
28
27, 28,
40, 41,
44
AV
EE
-
-5.2V
16
15
23
22
CLK
CLK
I
ECL
DGND, DGND1
R
R
CLK
CLK
R
R
Input Complementary to CLK.
When open pulled down to -1.3V.
Device is operable without CLK
input, but use of complementary
inputs of CLK and CLK is
recommended to obtain stable
high speed operation.
DV
EE
R
R
3, 12
-
DGND
-
0V
Digital GND (used for internal
circuits and output transistors).
Digital GND (used for internal
circuits and output transistors).
Digital GND (used for output
buffers).
Digital V
EE
. Internally connected
to AV
EE
(resistance: 4Ω to 6Ω).
Bypass with 0.1µF to DGND
LSB of Data Outputs. External
pull-down resistor is required.
Data Outputs. External pull-down
resistors are required.
D1
-
5, 19
DGND1
-
0V
-
6, 16
DGND2
-
0V
2, 13
4, 20
DV
EE
-
-5.2V
4
8
D0
O
ECL
DGND
5
6
7
8
9
10
11
9
10
11
12
13
14
15
D1
D2
D3
D4
D5
D6
D7
DV
EE
MSB of Data Outputs. External
pull-down resistor is required.
3
HI1386
Pin Descriptions
PIN NUMBER
DIP
1
LCC
3
SYMBOL
LINV
I/O
I
(Continued)
STANDARD
VOLTAGE
LEVEL
ECL
DGND, DGND1
EQUIVALENT CIRCUIT
DESCRIPTION
Input Pin for D0 (LSB) to D6
Output Polarity Inversion (see A/D
Output Code Table). Pulled low
when left open.
14
21
MINV
I
ECL
R
R
LINV
OR
MINV
R
-1.3V
Input Pin for D7 (MSB) Output
Polarity Inversion (see A/D Output
Code Table). Pulled low when left
open.
DV
EE
R
20, 24
32, 36
V
IN
I
V
RT
to V
RB
AGND
V
IN
V
IN
Analog Input Pins. These two pins
must be connected externally,
since they are not internally
connected. See Application Note
for precautions.
AV
EE
17
26
V
RB
I
-2V
V
RT
R1
R/2
Reference Voltage (Bottom).
Typically -2V. Bypass with a
0.1µF and 10µF to AGND.
R
COMPARATOR 1
R
22
34
V
RM
I
V
RB
/2
Reference Voltage Mid Point.
Can be used as a pin for integral
linearity compensation.
Reference Voltage (Top) Typical-
ly 0V.
27
42
V
RT
I
0V
R
V
RM
R2
R
COMPARATOR 2
COMPARATOR 127
COMPARATOR 128
R
COMPARATOR 129
R
COMPARATOR 130
R
COMPARATOR 255
V
RB
R3
R/2
4
HI1386
Absolute Maximum Ratings
T
A
= 25
o
C
Supply Voltage (AV
EE
, DV
EE
) . . . . . . . . . . . . . . . . . . . -7V to +0.5V
Analog Input Voltage (V
IN
) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V
Reference Input Voltage
V
RT
, V
RB
, V
RM
. . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V
|V
RT
-V
RB
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V
Digital Input Voltage
CLK, CLK, MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V
|CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V
V
RM
Pin Input Current (I
VRM
) . . . . . . . . . . . . . . . . . . -3mA to +3mA
Digital Output Current (ID0 to ID7) . . . . . . . . . . . . . . . -30mA to 0mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JAo
C/W
θ
JCo
C/W
PDIP Package . . . . . . . . . . . . . . . . . . .
58
N/A
CLCC Package . . . . . . . . . . . . . . . . . .
45
11
Maximum Junction Temperature
CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range (T
STG
) . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300
o
C
Operating Conditions
Temperature Ranges (Note 4)
PDIP Package (T
A
). . . . . . . . . . . . . . . . . . . . . . . . . -20
o
C to 75
o
C
CLCC Package (T
C
) . . . . . . . . . . . . . . . . . . . . . . . -20
o
C to100
o
C
Supply Voltage
AV
EE
, DV
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V
AV
EE
- DV
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V
AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V
Reference Input Voltage
V
RT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V
V
RB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V
Analog Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . V
RB
to V
RT
Pulse Width of Clock
t
PW1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6ns (Min)
t
PW0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6ns (Min)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
DYNAMIC CHARACTERISTICS
T
A
= 25
o
C, AV
EE
= DV
EE
= -5.2V, V
RT
= 0V, V
RB
= -2V (Note 1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
-
f
C
= 75MHz
f
C
= 75MHz
-
-
8
±0.3
±0.3
-
±0.5
±0.5
Bits
LSB
LSB
Signal to Noise and Distortion Ratio, SINAD Input = 1MHz, Full Scale
f
C
= 75MHz
RMS Signal
= -----------------------------------------------------------------
-
RMS Noise
+
Distortion
Input = 18.75MHz, Full Scale
f
C
= 75MHz
Error Rate
Differential Gain Error, DG
Differential Phase Error, DP
Maximum Conversion Rate, f
C
Aperture Jitter, t
AJ
Sampling Delay, t
DS
ANALOG INPUT
Input Bandwidth
Analog Input Capacitance, C
IN
Analog Input Resistance, R
IN
Input Bias Current, I
IN
REFERENCE INPUTS
Reference Resistance, R
REF
V
IN
= -1V
V
IN
= 2V
P-P
(-3dB)
V
IN
= 1V + 0.07V
RMS
Input = 18.749MHz, Full Scale
Error > 16 LSB, f
C
= 75MHz
NTSC 40 IRE Mod. Ramp,
f
C
= 75 MSPS
Error Rate of 10
-9
TPS (Note 2)
-
-
-
-
-
75
-
-
46
40
-
1.0
0.5
-
10
3.0
-
-
10
-9
-
-
-
-
-
dB
dB
TPS
(Note 2)
%
Degree
MSPS
ps
ns
150
-
-
-
-
17
390
-
-
-
-
200
MHz
pF
kΩ
µA
75
110
155
Ω
5
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