®
Pb
October 25, 2005
ea
- Fr e
o HS
nd R
iant
m pl
Co
NOT
R
R
D FO 9
NDE
17
MME ee HI1
O
S
EC
NE W
NS
ESIG
D
HI1176
8-Bit, 20 MSPS, Flash A/D Converter
Description
The HI1176 is an 8-bit, CMOS analog-to-digital converter for
video use that features a sync clamp function. The adoption
of a 2-step parallel method realizes low power consumption
and a maximum conversion speed of 20 MSPS. For higher
sampling rates, refer to the pin-for-pin compatible HI1179
data sheet, document number 3666.
Features
• Resolution
±0.5
LSB (DNL) . . . . . . . . . . . . . . . . . . . 8-Bit
•
/Title (HI1176)
[
Maximum Sampling Frequency . . . . . . . . . . . 20 MSPS
/Subject (8-Bit, 20 MSPS,
20 MSPS (Typ)
• Low Power Consumption at
Flash A/D Converter)
(Reference
/Author ()
Current Excluded) . . . . . . . . . . . . . . . 60mW
/Keywords (Harris
Function
• Built-In Sync Clamp
Semiconductor,
Video, Image Scan-
ner, PC
Monostable Multivibrator for
Clamp, Internal Ref-
• Built-In
Video capture, Set top box,
Clamp Pulse
Applications
erence)
Generation
• Video Digitizing
/Creator ()
Pulse Polarity Selection Function
• Built-In Sync
• Image Scanners
/DOCINFO pdfmark
• Clamp Pulse Direct Input Possible
•
/PageMode /UseOutlines
[
Built-In Clamp ON/OFF Function
• Built-In Reference Voltage Self Bias Circuit
/DOCVIEW pdfmark
• Input CMOS Compatible
• Three-State TTL Compatible Output
• Single +5V Power Supply
• Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . 11pF
• Reference Impedance (Typ) . . . . . . . . . . . . . . . . . 300Ω
• Direct Replacement for the Sony CXD1176
HI1176JCQ
HI1176-EV
• Low Cost High Speed Data Acquisition Systems
• Multimedia
Ordering Information
PART
NUMBER
TEMP. RANGE
(
o
C)
-40 to 85
25
PACKAGE
32 Ld MQFP
PKG. NO.
Q32.7x7-S
Evaluation Board
Pinout
HI1176
(MQFP)
TOP VIEW
DV
SS
DV
SS
V
RBS
V
REF
CCP
CLE
NC
OE
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
V
RB
AV
SS
AV
SS
V
IN
AV
DD
AV
DD
V
RT
V
RTS
NC
DV
DD
DV
DD
SYNC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1998, 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
AV
DD
CLK
SEL
PW
FN3582.6
HI1176
Functional Block Diagram
28
OE 30
DV
SS
31
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
1
2
3
4
5
6
7
8
UPPER
DATA
LATCHES
LOWER
DATA
LATCHES
LOWER
ENCODER
(4-BIT)
LOWER SAMPLING
COMPARATOR
(4-BIT)
DV
SS
REFERENCE SUPPLY
25 V
RBS
24 V
RB
23 AV
SS
22 AV
SS
21 V
IN
LOWER
ENCODER
(4-BIT)
LOWER SAMPLING
COMPARATOR
(4-BIT)
20 AV
DD
19 AV
DD
18 V
RT
UPPER
ENCODER
(4-BIT)
UPPER SAMPLING
COMPARATOR
(4-BIT)
17 V
RTS
16 AV
DD
DV
DD
10
DV
DD
11
CLK 12
CLOCK GENERATOR
NC
9
-
+
15 PW
14 SYNC
M•M
29
27
26
13 SEL
NC 32
CLE CCP V
REF
Typical Application Schematic
WHEN CLAMP IS NOT USED (SELF BIAS USED)
+5V (DIGITAL)
HCO4
CLOCK IN
0.1µF
+5V (ANALOG)
0.01µF
16 15 14 13 12 11 10 9
8
17
18
19
20
7
6
5
4
3
2
D7
D6
D5
D4
D3
D2
D1
D0
VIDEO IN
75Ω
0.1µF
10pF
0.01µF
21
22
23
1
24
25 26 27 28 29 30 31 32
GND (ANALOG)
+5V (DIGITAL)
GND (DIGITAL)
2
HI1176
Absolute Maximum Ratings
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Reference Voltage, V
RT
, V
RB
. . . . . . . . . V
DD
+ 0.5V to V
SS
- 0.5V
Analog Input Voltage, V
IN
. . . . . . . . . . . . V
DD
+ 0.5V to V
SS
- 0.5V
Digital Input Voltage, CLK . . . . . . . . . . . . V
DD
+ 0.5V to V
SS
- 0.5V
Digital Output Voltage, V
OH
, V
OL
. . . . . . V
DD
+ 0.5V to V
SS
- 0.5V
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
Operating Conditions
(Note 1)
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Supply Voltage
AV
DD
, AV
SS
, DV
DD
, DV
SS
. . . . . . . . . . . . . . . +4.75V to +5.25V
|DGND-AGND| . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mV to 100mV
Reference Input Voltage
V
RB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V and Above
V
RT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V and Below
Analog Input Voltage, V
IN
. . . . . . . . V
RB
to V
RT
(1.8V
P-P
to AV
DD
)
Clock Pulse Width
t
PW1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
t
PW0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Offset Voltage
E
OT
E
OB
Integral Non-Linearity, INL
Differential Non-Linearity, DNL
DYNAMIC CHARACTERISTICS
f
C
= 20 MSPS, V
DD
= +5V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C (Note 1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
-60
+20
f
C
= 20 MSPS, V
IN
= 0.5V to 2.5V
f
C
= 20 MSPS, V
IN
= 0.5V to 2.5V
-
-
-40
+40
±0.5
±0.3
-20
+60
±1.3
±0.5
mV
mV
LSB
LSB
Signal to Noise Ratio, SINAD
RMS Signal
---------------------------------------------------------------------------------------------------------------
-
Signal-To-Noise + Distortion Ratio, SINAD
Maximum Conversion Speed, f
C
Minimum Conversion Speed
Differential Gain Error, DG
Differential Phase Error, DP
Aperture Jitter, t
AJ
Sampling Delay, t
DS
ANALOG INPUTS
Analog Input Bandwidth (-1dB), BW
Analog Input Capacitance, C
IN
f
S
= 20MHz, f
IN
= 1MHz
f
S
= 20MHz, f
IN
= 3.58MHz
V
IN
= 0.5V to 2.5V, f
IN
= 1kHz Ramp
-
-
20
-
46
46
35
-
1.0
0.5
30
4
-
-
-
0.5
-
-
-
-
dB
dB
MSPS
MSPS
%
Degree
ps
ns
NTSC 40 IRE Mod Ramp, f
C
= 14.3 MSPS
-
-
-
-
-
V
IN
= 1.5V + 0.07V
RMS
-
18
11
-
-
MHz
pF
3
HI1176
Electrical Specifications
PARAMETER
REFERENCE INPUT
Reference Pin Current, I
REF
Reference Resistance (V
RT
to V
RB
), R
REF
INTERNAL VOLTAGE REFERENCES
Self Bias
V
RB
V
RT
- V
RB
DIGITAL INPUTS
Digital Input Voltage
V
IH
V
IL
Digital Input Current
I
IH
I
IL
DIGITAL OUTPUTS
Digital Output Current
I
OH
I
OL
Digital Output Current
I
OZH
I
OZL
TIMING CHARACTERISTICS
Output Data Delay, t
DL
POWER SUPPLY CHARACTERISTIC
Supply Current, I
DD
CLAMP CHARACTERISTICS
Clamp Offset Voltage, E
OC
V
IN
= DC, PWS = 3µs
V
REF
= 0.5V
V
REF
= 2.5V
Clamp Pulse Width (Sync Pin Input), t
CPW
Clamp Pulse Delay, t
CPD
NOTE:
1. Electrical specifications guaranteed only under the stated operating conditions.
C = 100pF, R = 130kΩ on Pin 15
0
-50
1.75
-
+20
-30
2.75
25
+40
-10
3.75
-
mV
mV
µs
ns
f
C
= 20 MSPS, NTSC Ramp Wave Input
-
12
18
mA
-
18
30
ns
OE = V
DD
, V
DD
= Max
V
OH
= V
DD
V
OL
= 0V
-
-
-
-
16
16
µA
µA
OE = V
SS
, V
DD
= Min
V
OH
= V
DD
-0.5V
V
OL
= 0.4V
-1.1
3.7
-
-
-
-
mA
mA
V
DD
= Max
V
IH
= V
DD
V
IL
= 0V
-
-
-
-
5
5
µA
µA
4.0
-
-
-
-
1.0
V
V
Short V
RB
and V
RBS
, Short V
RT
and V
RTS
0.48
1.96
0.52
2.08
0.56
2.22
V
V
4.5
230
6.6
300
8.7
450
mA
Ω
f
C
= 20 MSPS, V
DD
= +5V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C (Note 1)
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
HI1176
Timing Diagrams
t
PW1
t
PW0
CLOCK
ANALOG INPUT
N
N+1
N-2
N-1
N+3
N
N+4
N+1
DATA OUTPUT
N-3
N-2
: POINT FOR ANALOG SIGNAL SAMPLING
t
D
= 18ns
FIGURE 1.
V
I
(1)
V
I
(2)
V
I
(3)
V
I
(4)
ANALOG INPUT
EXTERNAL CLOCK
UPPER COMPARATOR BLOCK
S (1)
C (1)
S (2)
C (2)
S (3)
C (3)
S (4)
C (4)
UPPER DATA
MD (0)
MD (1)
MD (2)
MD (3)
LOWER REFERENCE VOLTAGE
RV (0)
RV (1)
RV (2)
RV (3)
LOWER COMPARATOR BLOCK A
S (1)
H (1)
C (1)
S (3)
H (3)
C (3)
LOWER DATA A
LD (-1)
LD (1)
LOWER COMPARATOR BLOCK B
H (0)
C (0)
S (2)
H (2)
C (2)
S (4)
H (4)
LOWER DATA B
LD (-2)
LD (0)
LD (2)
DIGITAL OUTPUT
OUT (-2)
OUT (-1)
OUT (0)
OUT (1)
FIGURE 2.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
