CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution, n
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, V
OS
AV
DD
= +4.75V to +5.25V, DV
DD
= +4.75 to +5.25V, V
REF
= +2.0V, f
S
= 40MHz,
CLK Pulse Width = 12.5ns, T
A
= 25
o
C (Note 4)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
f
S
= 40MHz (End Point)
f
S
= 40MHz
(Note 2)
(Note 2)
-0.5
-
-
-
-
1.9
0.5
8
-
-
-
-
10
2.0
2.0
-
1.3
0.25
1
13
15
2.1
2.1
Bits
LSB
LSB
mV
LSB
mA
V
V
Full Scale Error, FSE (Adjustable to Zero)
Full Scale Output Current, I
FS
Full Scale Output Voltage, V
FS
Output Voltage Range, V
FSR
DYNAMIC CHARACTERISTICS
Throughput Rate
Glitch Energy, GE
Differential Gain,
A
V
(Note 3)
Differential Phase,
(Note 3)
REFERENCE INPUT
Voltage Reference Input Range
Reference Input Resistance
DIGITAL INPUTS
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic Current, I
IL
, I
IH
Digital Input Capacitance, C
IN
TIMING CHARACTERISTICS
Data Setup Time, t
SU
Data Hold Time, t
HLD
See Figure 7
R
OUT
= 75
40.0
-
-
-
-
30
1.2
0.5
-
-
-
-
MHz
pV-s
%
Degree
0.5
(Note 3)
1.0
-
-
2.0
-
V
M
(Note 3)
(Note 3)
(Note 3)
(Note 3)
3.0
-
-
-
-
-
-
5.0
-
1.5
5.0
-
V
V
A
pF
See Figure 1
See Figure 1
5
10
-
-
-
-
ns
ns
FN3662 Rev.3.00
October 26, 2005
Page 3 of 7
HI1171
Electrical Specifications
PARAMETER
Propagation Delay Time, t
PD
Settling Time, t
SET
(to
1
/
2
LSB)
CLK Pulse Width, t
PW1
, t
PW2
POWER SUPPLY CHARACTERISITICS
IAV
DD
IDV
DD
Power Dissipation
NOTES:
2. Excludes error due to external reference drift.
3. Parameter guaranteed by design or characterization and not production tested.
4. Electrical specifications guaranteed only under the stated operating conditions.
14.3MHz, at Color Bar Data Input
14.3MHz, at Color Bar Data Input
200 load at 2V
P-P
Output
-
-
-
10.9
4.2
-
11.5
4.8
80
mA
mA
mW
AV
DD
= +4.75V to +5.25V, DV
DD
= +4.75 to +5.25V, V
REF
= +2.0V, f
S
= 40MHz,
CLK Pulse Width = 12.5ns, T
A
= 25
o
C (Note 4)
(Continued)
TEST CONDITIONS
See Figure 9
See Figure 1
See Figure 1
MIN
-
-
12.5
TYP
10
10
-
MAX
-
15
-
UNITS
ns
ns
ns
Timing Diagram
t
PW1
t
PW2
CLK
t
SU
t
HLD
DATA
t
SU
t
HLD
t
SU
t
HLD
t
PD
100%
D/AOUT
50%
t
PD
t
PD
0%
FIGURE 1.
FN3662 Rev.3.00
October 26, 2005
Page 4 of 7
HI1171
Typical Performance Curves
OUTPUT FULL SCALE VOLTAGE (V)
200
2
GLITCH ENERGY (pV/s)
V
DD
= 5.0V, R = 200
16R = 3.3k, T
A
= 25
o
C
1
REFERENCE VOLTAGE (V)
2
100
OUTPUT RESISTANCE ()
200
OUTPUT FULL SCALE VOLTAGE (V)
2.0
1.9
V
DD
= 5.0V, V
REF
= 2.0V
R = 20016R = 3.3k
T
A
= 25
o
C
0
-25
0
25
50
75
100
1
FIGURE 2. OUTPUT FULL SCALE VOLTAGE vs REFERENCE
VOLTAGE
FIGURE 3. OUTPUT RESISTANCE vs GLITCH ENERGY
AMBIENT TEMPERATURE (
o
C)
FIGURE 4. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE
Pin Descriptions
24 PIN
SOIC
1-8
9
10, 13
11
12
14
15
16
17
18, 19, 22
20
PIN
NAME
D0(LSB) thru
D7(MSB)
BLNK
DV
SS
VB
CLK
AV
SS
I
REF
V
REF
VG
AV
DD
I
OUT1
PIN DESCRIPTION
Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 7, the Most Significant Bit.
Blanking Line, used to clear the internal data register to the zero condition when High, normal operation when Low.
Digital Ground.
Voltage Bias, connect a 0.1F capacitor to DV
SS
.
Data Clock Pin 100kHz to 40MHz.
Analog Ground.
Current Reference, used to set the current range. Connect a resistor to AV
SS
that is 16 times greater than the re-
sistor on I
OUT1
. (See Typical Applications Circuit).
Input Reference Voltage used to set the output full scale range.
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