COM20051+
Integrated Microcontroller and Network
Interface with Watchdog Timer and A/D
Converter Interface
FEATURES
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Low Cost
Microcontroller Based on Popular 8051
Architecture
Intel 8051 Code Compatible
68 Pin PLCC
Network Supports up to 255 Nodes
Powerful Network Diagnostics
Maximum 512 Byte Packets
Duplicate Node ID Detection
Self-Configuring Network Protocol
Retains all 8051 Peripherals Including
Serial I/O and Two Timers
Utilizes ARCNET® Token Bus Network
Engine
Requires No Special Emulators
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5 Mbps to 156 Kbps Network Data Rate
Network Interface Supports RS-485,
Twisted Pair, Coaxial, and Fiber Optic
Interfaces
Receive All Mode Allows Any Packet to Be
Received
On-Board Programmable Watchdog Timer
Analog Data Acquisition Port
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Interfaces to Any A/D Converter up to
16 Bits Wide
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Sampling Rates from 1 s to 100ms
Possible
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Decouples 80C32 from Repetitive
Sampling Tasks
GENERAL DESCRIPTION
The COM20051+ is a low-cost, highly-integrated
microcontroller
incorporating
a
high-
performance network controller based on the
ARCNET Token Bus Standard (ANSI 878.1).
The COM20051+ is based around the popular
Intel 8051 architecture.
The device is
implemented using a microcontroller core
similar to the Intel 80C32 ROMless version of
the 8051 architecture. The COM20051+ is ideal
for distributed control networking applications
such as those found in industrial/machine
controls, building/factory automation, consumer
products, instrumentation, and automobiles.
The COM20051+ contains many features that
are
beneficial
for
embedded
control
applications. The microcontroller is a fully-
functional 16MHz 80C32 that is comparable to
the Intel 80C32. In contrast to other embedded
controller/networking solutions, the COM20051+
adds a fully-featured, robust, powerful, and
simple network interface, watchdog timer, and
data acquisition port, while retaining all of the
basic 8051 peripherals, such as the serial port
and counter/timers.
TABLE OF CONTENTS
FEATURES .......................................................................................................................................1
GENERAL DESCRIPTION.................................................................................................................1
PIN CONFIGURATION ......................................................................................................................3
OVERVIEW .......................................................................................................................................4
DESCRIPTION OF PIN FUNCTIONS ................................................................................................5
BASIC ARCHITECTURE ...................................................................................................................8
PROTOCOL DESCRIPTION............................................................................................................ 14
NETWORK PROTOCOL............................................................................................................ 14
DATA RATES ............................................................................................................................ 14
NETWORK RECONFIGURATION ............................................................................................. 14
BROADCAST MESSAGES ........................................................................................................ 16
EXTENDED TIMEOUT FUNCTION ............................................................................................ 16
LINE PROTOCOL...................................................................................................................... 17
SYSTEM DESCRIPTION .................................................................................................................. 20
MICROCONTROLLER INTERFACE .......................................................................................... 20
TRANSMISSION MEDIA INTERFACE ....................................................................................... 20
ARCNET CORE FUNCTIONAL DESCRIPTION ................................................................................ 28
MICROSEQUENCER................................................................................................................. 28
INTERNAL REGISTERS ............................................................................................................ 28
INTERNAL RAM ........................................................................................................................ 40
COMMAND CHAINING .............................................................................................................. 44
RESET DETAILS ....................................................................................................................... 47
INITIALIZATION SEQUENCE .................................................................................................... 47
IMPROVED DIAGNOSTICS....................................................................................................... 48
COM20051+ APPLICATIONS INFORMATION .................................................................................. 60
USING ARCNET DIAGNOSTICS TO OPTIMIZE YOUR SYSTEM ..................................................... 78
CABLING THE COM20051+ ............................................................................................................. 82
USING THE COM20051+'S EMULATION MODE .............................................................................. 83
OPERATIONAL DESCRIPTION........................................................................................................ 84
MAXIMUM GUARANTEED RATINGS ........................................................................................ 84
DC ELECTRICAL CHARACTERISTICS ..................................................................................... 84
TIMING DIAGRAMS .................................................................................................................. 86
80 Arkay Drive
Hauppauge, NY 11788
(516) 435-6000
FAX (516) 273-3123
2
In addition, the COM20051+ supports an
Emulation Mode that permits the use of a
standard 80C32 emulator in conjunction with the
COM20051+ to develop software drivers for the
network core.
This mode is achieved by
mapping the ARCNET network core into a 256-
byte page of the External Data Memory space of
the 80C32 instead of the SFR area, which would
require a costly adapter for the emulator.
The networking core is based around an
ARCNET Token Bus protocol engine that
provides highly-reliable and fault tolerant
message delivery at data rates ranging
from 5Mbps down to 156 Kbps with message
sizes varying from 1 to 508 bytes. The
ARCNET protocol offers a simple, standardized,
and easily-understood networking solution for
any application. The network interface supports
several media interfaces, including RS-485,
coaxial, and twisted pair in either bus or star
topologies. The network interface incorporates
powerful diagnostic features for network
management and fault isolation. These include
duplicate node ID detection, reconfiguration
detection, receive all (monitor) mode, receiver
activity, and token detection.
ARCNET is a registered trademark of Datapoint Corporation
PIN CONFIGURATION
nNIDCS
TXLED
RXIN
VCC
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P0.0
P0.1
P0.2
P0.3
9
P1.6
P1.7
RESET
N/C
N/C
VCC
N/C
VSS
N/C
P3.0
N/C
nPULSE1
P3.1
P3.2
P3.3
P3.4
P3.5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
8
7 6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
P0.5
P0.6
P0.7
nEA/EMUL
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
TXEN
ALE
nPSEN
P2.7
P2.6
COM20051+
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
nEOC
nPULSE2
P2.0
TURBO
HBE
LBE
P3.6
P3.7
P2.1
P2.2
P2.3
P2.4
XTAL2
XTAL1
START
P2.5
VSS
Package: 68-Pin PLCC
3
P0.4
VSS
N/C
OVERVIEW
The COM20051+ is essentially a data
acquisition/network board-in-a-chip. It takes an
80C32-like microcontroller core, an ARCNET
controller, a watchdog timer, and an analog data
acquisition port and integrates them into a
single device. ARCNET is a token passing-
based protocol that combines powerful flow
control, error detection, and diagnostic
capabilities to deliver fast and reliable
messages. The COM20051+ supports a variety
of data rates (5 Mbps to 156 Kbps), topologies
(bus, star, tree), and media types (RS-485,
coax, twisted pair, fiber optic, and powerline) to
suit any type of application.
The ARCNET network core of the COM20051+
contains many features that make network
development simple and easy to comprehend.
Diagnostic features, such as Receive All,
Duplicate
ID
Detection,
Reconfiguration
Detection, Token, and Receiver Detection, all
combine to make the COM20051+ simple to use
and to implement in any environment. The
ARCNET protocol itself is relatively simple to
understand and very flexible. A wide variety of
support products are available to assist in
network development, such as software drivers,
line drivers, boards, and development kits. The
COM20051+ implements a full-featured 16MHz,
Intel code-compatible 80C32-like microcontroller
with all of the standard peripheral functions,
including a full duplex serial port, two
timer/counters, one 8-bit general purpose digital
I/O port, and interrupt controller. The 8051
architecture has long been a standard in the
embedded control industry for low-level data
acquisition and control. ARCNET and the 8051
form a simple solution for many of today's and
tomorrow's low-level networking solutions.
The COM20051+ also includes a programmable
watchdog timer for fail-safe operation. The
watchdog timer has programmable timeout
values ranging from 3.3ms to 6.5s, with a
programmable reset feature (either a pulsed
reset or reset and hold). A full analog data
acquisition port is also included in the
COM20051+.
The data acquisition port
interfaces to most types of parallel A/D
converters. The data acquisition port provides
all the handshaking and data buffering fuctions
normally associated with repetitive sampling
tasks. An internal 32-byte FIFO buffers the
samples in chronological order and interrupts
the processor at a programmed limit.
Offloading repetitive sampling and buffering
tasks frees the microcontroller core tasks such
as data formatting and processing and
communications tasks.
In addition to the 80C32 and the ARCNET
network core, the COM20051+ contains all the
address decoding and interrupt routing logic to
interface the network core, the watchdog timer,
and the data acquisition port to the 80C32 core.
The integrated 8051/ARCNET combination
provides an extremely cost-effective and space-
efficient solution for industrial networking
applications. The COM20051+ can be used in a
stand-alone embedded application, executing
control
algorithms
or
performing
data
acquisition and communicating data in a
master/slave or peer/peer configuration, or used
as a slave processor handling communication
tasks in a multi-processing system.
4
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1
4-11
12
19
21
NAME
Receive In
P1.0-1.7
Reset
P3.0
nPulse 1
SYMBOL
RXIN
P1.0-1.7
RESET
P3.0
nPULSE1
DESCRIPTION
Input. Network receiver input.
Input/Output. Port 1 of the 80C32. General
purpose digital I/O port.
Input. Active high reset.
Input/Output. Port 3 bit 0 of the 8051. RX input of
serial port.
Output. Network output. Open-drain when
backplane mode is invoked, otherwise it is a push-
pull output.
Input/Output. Port 3 bits 1-7 of the 8051.
Input. Oscillator input 1.
Input. Oscillator input 2.
Ground pin.
Output. Network output. Outputs a synchronous
clock at 2x the data rate when backplane mode is
invoked.
Input/Output. Port 2 of the 8051. High order
address bus.
Output.
Output.
Output. Active high signal that goes active
whenever data is being transmitted. This signal will
remain low whenever the TXEN bit of the network
controller is reset.
Input. When high, causes the 8051's outputs to tri-
state. When low, allows the 8051 to address
external memory. Must be low to execute code
from the embedded 8051.
Input/Output. Port 0 of the 8051. Multiplexed low
order address/data bus.
22-28
30
29
3,17,31
37
P3.1-3.7
Crystal
Oscillator
Crystal
Oscillator
Ground
nPulse 2
P3.1-3.7
XTAL1
XTAL2
VSS
nPULSE2
38-45
46
47
48
P2.0-2.7
P2.0-2.7
nProgram Store nPSEN
Enable
Address Latch
Enable
Transmit
Enable
ALE
TXEN
57
nExternal
nEA/EMUL
Address
Enable/Emulate
Enable
P0.7-0.0
P0.7-0.0
58-65
5
编程基础
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