HS-82C55ARH
TM
Data Sheet
August 2000
File Number
3191.2
Radiation Hardened CMOS Programmable
Peripheral Interface
The Intersil HS-82C55ARH is a high performance, radiation
hardened CMOS version of the industry standard 8255A and
is manufactured using a hardened field, self-aligned silicon
gate CMOS process. It is a general purpose programmable
I/O device which may be used with many different
microprocessors. There are 24 I/O pins which are organized
into two 8-bit and two 4-bit ports. Each port may be
programmed to function as either an input or an output.
Additionally, one of the 8-bit ports may be programmed for
bidirectional operation, and the two 4-bit ports can be
programmed to provide handshaking capabilities. The high
performance, radiation hardness, and industry standard
configuration of the HS-82C55ARH make it compatible with
the HS-80C86RH radiation hardened microprocessor.
Static CMOS circuit design insures low operating power. Bus
hold circuitry eliminates the need for pull-up resistors. The
Intersil hardened field CMOS process results in performance
equal to or greater than existing radiation resistant products
at a fraction of the power.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95819. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Features
• Electrically Screened to SMD # 5962-95819
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . . . . <10
8
rad(Si)/s
- Latch Up Free EPI-CMOS
• Low Power Consumption
- IDDSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µA
• Pin Compatible with NMOS 8255A and the Intersil 82C55A
• High Speed, No “Wait State” Operation with 5MHz
HS-80C86RH
• 24 Programmable I/O Pins
• Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up
Resistors
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process
• Single 5V Supply
• 2.0mA Drive Capability on All I/O Port Outputs
• Military Temperature Range . . . . . . . . . . . -55
o
C to 125
o
C
Pinout
CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T40
TOP VIEW
PA3
PA2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 PA4
39 PA5
38 PA6
37 PA7
36 WR
35 RESET
34 D0
33 D1
32 D2
31 D3
30 D4
29 D5
28 D6
27 D7
26 VDD
25 PB7
24 PB6
23 PB5
22 PB4
21 PB3
Ordering Information
ORDERING NUMBER
5962R9581901QQC
5962R9581901VQC
INTERNAL
MKT. NUMBER
HS1-82C55ARH-8
HS1-82C55ARH-Q
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
PA1
PA0
RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright © Intersil Corporation 2000
HS-82C55ARH
Pin Descriptions
SYMBOL
PA0-7
PIN
NUMBERS
1-4, 37-40
TYPE
I/O
DESCRIPTION
Port A:
General purpose I/O Port. Data direction and mode is determined by the contents of the
Control Word.
Port B:
General purpose I/O port. See Port A.
Port C (Lower):
Combination I/O port and control port associated with Port B. See Port A.
Port C (Upper):
Combination I/O Port and control port associated with Port A. See Port A.
Bidirectional Data Bus:
Three-State data bus enabled as an input when CS and WR are low and
as an output when CS and RD are low.
VDD:
The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is recommended for
decoupling.
Ground.
Chip Select:
A “low” on this input pin enables the communication between the HS-82C55ARH
and the CPU.
Read:
A “low” on this input pin enables the HS-82C55ARH to send the data or status information
to the CPU on the data bus. In essence, it allows the CPU to “read from” the HS-82C55ARH.
Write:
A “low” on this input pin enables the CPU to write data or control words into the
HS-82C55ARH.
Port Select 0 and Port Select 1:
These input signals, in conjunction with the RD and WR inputs,
control the selection of one of the three ports or the control word registers. They are normally
connected to the Least Significant Bits of the address bus (A0 and A1).
Reset:
A “high” on this input clears the control register and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the HS-82C55ARH will hold the I/O port inputs to a logic “1”
state with a maximum hold current of 400µA.
PB0-7
PC0-3
PC4-7
D0-7
18-25
14-17
10-13
27-34
I/O
I/O
I/O
I/O
VDD
26
I
GND
CS
7
6
I
I
RD
5
I
WR
36
I
A0 and A1
8, 9
I
Reset
35
I
2
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