Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> USB97C201-MN

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USB97C201-MN: 产品描述USB 2.0 ATA/ ATAPI Controller; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小437KB，共59页; 制造商SMSC; 官网地址http://www.smsc.com/

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USB97C201-MN概述

USB 2.0 ATA/ ATAPI Controller

USB97C201-MN规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	SMSC
零件包装代码	QFP
包装说明	LFQFP,
针数	100
Reach Compliance Code	unknow
其他特性	ALSO REQUIRES 3.3V SUPPLY
地址总线宽度	16
总线兼容性	IDE
最大时钟频率	12 MHz
最大数据传输速率	66 MBps
外部数据总线宽度	8
JESD-30 代码	S-PQFP-G100
JESD-609代码	e0
长度	12 mm
端子数量	100
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	235
认证状态	Not Qualified
座面最大高度	1.6 mm
最大供电电压	2.75 V
最小供电电压	2.25 V
标称供电电压	2.5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	GULL WING
端子节距	0.4 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	12 mm
uPs/uCs/外围集成电路类型	BUS CONTROLLER, UNIVERSAL SERIAL BUS

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USB97C201

Rev 1.6

USB 2.0 ATA/ ATAPI Controller

FEATURES

2.5 Volt, Low Power Core Operation

3.3 Volt I/O with 5V input tolerance

Complete USB Specification 2.0 Compatibility

Includes USB 2.0 Transceiver

A Bi-directional Control, a Bi-directional

Interrupt, and a Bi-directional Bulk Endpoint

are provided.

Complete System Solution for interfacing ATA or

ATAPI devices to USB 2.0 bus

Supports USB Mass Storage Compliant

Bootable BIOS

Support for ATAPI Devices:

CD-ROM

CD-R

CD-RW

DVD

DVD/R/W

8051 8 bit microprocessor

Provides low speed control functions

30 Mhz execution speed at 4 cycles per

instruction average

768 Bytes of internal SRAM for general

purpose scratchpad or program execution

while re-flashing external ROM

Double Buffered Bulk Endpoint

Bi-directional 512 Byte Buffer for Bulk Endpoint

64 Byte RX Control Endpoint Buffer

64 Byte TX Control Endpoint Buffer

64 Byte TX Interrupt Endpoint Buffer

64 Byte RX Interrupt Endpoint Buffer

External Program Memory Interface

64K Byte Code Space

Flash, SRAM, or EPROM Memory

On Board 12Mhz Crystal Driver Circuit

Internal PLL for 480Mhz USB2.0 Sampling, 30Mhz

MCU clock, and 60Mhz ATA clock

Supports firmware upgrade via USB bus if “boot

block” Flash program memory is used

8 GPIOs for special function use : LED indicators,

button inputs, etc.

Inputs capable of generating interrupts with

either edge sensitivity

One GPIO has automatic ½ sec toggle

capability for flashing an LED indicator.

100 Pin TQFP Package (14.0 x 14.0 mm footprint)

25% smaller body size than other 100 pin

TQFP Packages

100 Pin QFP Package

ORDERING INFORMATION

Order Number(s):

USB97C201-MN

for 100 pin TQFP package

USB97C201-MC

for 100 pin QFP package

SMSC USB97C201

Page 1

Rev. 11-05-03

DATASHEET

80 Arkay Drive

Hauppauge, NY 11788

(631) 435-6000

FAX (631) 273-3123

Standard Microsystems and SMSC are registered trademarks of Standard Microsystems Corporation. Product names and company names are the

trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications;

consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is

believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product

descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The

provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC

or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard

Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.

SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause

or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further

testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale

Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND

ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,

OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON

CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR

NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE

POSSIBILITY OF SUCH DAMAGES.

SMSC USB97C201

Page 2

Rev. 11-05-03

DATASHEET

TABLE OF CONTENTS

1.0

2.0

3.0

GENERAL DESCRIPTION ..............................................................................................................................6

PIN TABLE ......................................................................................................................................................7

PIN CONFIGURATION....................................................................................................................................8

3.1

4.0

5.0

QFP/TQFP 100 Pin.......................................................................................................................... 8

BLOCK DIAGRAM ..........................................................................................................................................9

PIN DESCRIPTIONS .....................................................................................................................................10

5.1

6.0

BUFFER TYPE DESCRIPTIONS .................................................................................................. 13

FUNCTIONAL BLOCK DESCRIPTIONS ......................................................................................................14

6.1 MCU ............................................................................................................................................... 14

6.1.1 MCU Memory Map: Code Space............................................................................................... 14

6.1.2 MCU Memory Map: XData Space ............................................................................................. 15

6.1.3 MCU Block Register Summary.................................................................................................. 16

6.1.4 MCU Register Descriptions ....................................................................................................... 19

6.2 SIE Block....................................................................................................................................... 42

6.2.1 Autonomous USB Protocol........................................................................................................ 43

6.2.2 USB Events ............................................................................................................................... 43

6.2.3 Standard Device Requests........................................................................................................ 44

6.2.4 SIE Configurations..................................................................................................................... 44

6.3 IDE Controller Description .......................................................................................................... 45

6.3.1 IDE Configurations..................................................................................................................... 45

6.3.2 PIO IDE Operations ................................................................................................................... 45

6.3.3 PIO IDE Data Prefetching and Posting...................................................................................... 46

6.3.4 DMA Transfers........................................................................................................................... 46

6.3.5 Ultra ATA/66 Synchronous DMA Operation .............................................................................. 46

6.3.6 Ultra ATA/66 Operation ............................................................................................................. 47

6.4 SRAM Buffers ............................................................................................................................... 48

6.5 8051 Options................................................................................................................................. 48

6.6 Address Multiplexing................................................................................................................... 48

6.7 SRAM Time Multiplexer Operation ............................................................................................. 49

6.7.1 Phase 0 (Ø0) ............................................................................................................................. 49

6.7.2 Phase 1 (Ø1) ............................................................................................................................. 49

6.7.3 Phase 2 (Ø2) ............................................................................................................................. 49

6.7.4 Phase 3 (Ø3) ............................................................................................................................. 50

6.8 EP2 SRAM Buffer Operation ....................................................................................................... 50

6.9 EP2 Automatic Buffer Operations .............................................................................................. 50

6.9.1 Receive Auto-Toggle ................................................................................................................. 50

6.9.2 Transmit Buffer Operation ......................................................................................................... 52

6.9.3 Automatic Transfer Operation ................................................................................................... 52

7.0

8.0

DC PARAMETERS........................................................................................................................................54

AC SPECIFICATIONS...................................................................................................................................56

8.1

8.2

9.0

10.0

ATA/ATAPI .................................................................................................................................... 56

USB2.0 Timing.............................................................................................................................. 56

PACKAGING .................................................................................................................................................57

USB97C201 REVISIONS ..............................................................................................................................59

SMSC USB97C201

Page 3

Rev. 11-05-03

DATASHEET

TABLES

Table 1 - USB97C201 Buffer Type Descriptions ..........................................................................................................13

Table 2 - MCU Code Memory Map ..............................................................................................................................14

Table 3 - MCU XData Memory Map .............................................................................................................................15

Table 4 - MCU Block Register Summary......................................................................................................................16

Table 5 - 8051 Core SFR Register Summary...............................................................................................................18

Table 6 - Interrupt 0 Source Register ...........................................................................................................................19

Table 7 - Interrupt 0 Mask ............................................................................................................................................20

Table 8 - Interrupt 1 Source Register ...........................................................................................................................20

Table 9 - Interrupt 1 Mask ............................................................................................................................................21

Table 10 - Device Revision Register ............................................................................................................................21

Table 11 - Device Identification Register......................................................................................................................21

Table 12 - GPIO Direction Register..............................................................................................................................22

Table 13 - GPIO Output Register .................................................................................................................................24

Table 14 - GPIO Input Register....................................................................................................................................24

Table 15 – GPIO Interrupt Status Register (INT4) .......................................................................................................24

Table 16 – GPIO Interrupt Mask Register ....................................................................................................................25

Table 17 - Utility Configuration Register.......................................................................................................................26

Table 18 – SRAM Data Port Register ..........................................................................................................................26

Table 19 – SRAM Address Register 1 .........................................................................................................................27

Table 20 – SRAM Address Register 2 .........................................................................................................................27

Table 21 - MCU Clock Source Select...........................................................................................................................27

Table 22 - Wakeup Source 1 Register (INT2) ..............................................................................................................28

Table 23 - Wakeup Mask 1 Register ............................................................................................................................28

Table 24 –USB Address Register ................................................................................................................................29

Table 25 – SIE Configuration Register .........................................................................................................................29

Table 26 - USB Bus Status Register ............................................................................................................................30

Table 27 – USB Bus Status Mask Register..................................................................................................................30

Table 28 – SIE Status Register ....................................................................................................................................31

Table 29 – SIE Status Mask Register ..........................................................................................................................31

Table 30 – USB Configuration Number Register..........................................................................................................32

Table 31 – Endpoint 0 Receive Control Register .........................................................................................................32

Table 32 – Endpoint 0 Transmit Control Register ........................................................................................................32

Table 33 – Endpoint 1 Receive Control Register .........................................................................................................32

Table 34 – Endpoint 1 Transmit Control Register ........................................................................................................33

Table 35 – Endpoint 2 Control Register .......................................................................................................................33

Table 36 – Endpoint 0 Receive Byte Count Register ...................................................................................................34

Table 37 – Endpoint 0 Transmit Byte Count Register ..................................................................................................35

Table 38 – Endpoint 1 Receive Byte Count Register ...................................................................................................35

Table 39 – Endpoint 1 Transmit Byte Count Register ..................................................................................................35

Table 40 – RAM Buffer Write Byte Count Register A1 .................................................................................................35

Table 41 – RAM BUFFER WRITE Byte Count Register A2 Register...........................................................................35

Table 42 – RAM Buffer Write Byte Count Register B1 .................................................................................................36

Table 43 – RAM Buffer Write Byte Count Register B2 Register...................................................................................36

Table 44 – RAM Buffer Read Byte Count Register A1 .................................................................................................36

Table 45 – RAM Buffer Read Byte Count Register A2 Register...................................................................................36

Table 46 – RAM Buffer Read Byte Count Register B1 .................................................................................................36

Table 47 – RAM Buffer Read Byte Count Register B2 Register...................................................................................36

Table 48 – NAK Register (INT5) ..................................................................................................................................36

Table 49 – NAK Mask Register ....................................................................................................................................37

Table 50 – USB Error Register.....................................................................................................................................37

Table 51 – MSB ATA Data Register.............................................................................................................................38

Table 52 – LSB ATA Data Register..............................................................................................................................38

Table 53 – ATA Transfer Count Register 0 ..................................................................................................................38

Table 54 – ATA Transfer Count Register 1 ..................................................................................................................38

Table 55 – ATA Transfer Count Register 2 ..................................................................................................................38

Table 56 – ATA Transfer Count Register 3 ..................................................................................................................39

Table 57 –ATA Control Register ..................................................................................................................................39

Table 58 –ATA Ultra DMA Timing Register..................................................................................................................40

Table 59 – IDE Timing Register ...................................................................................................................................40

Table 60 –ATA Slew Rate Control A Register..............................................................................................................42

Table 61 –ATA Slew Rate Control B Register..............................................................................................................42

Table 62 – IDE Transaction Timing..............................................................................................................................46

Table 63 – ULTRA ATA/66 Control Signal Assignments..............................................................................................47

Table 64 –Buffer SRAM Mapping.................................................................................................................................48

SMSC USB97C201

Page 4

Rev. 11-05-03

DATASHEET

USB97C201-MN相似产品对比

	USB97C201-MN	USB97C201	USB97C201-MC	USB97C201_03
描述	USB 2.0 ATA/ ATAPI Controller	USB 2.0 ATA/ ATAPI Controller	USB 2.0 ATA/ ATAPI Controller	USB 2.0 ATA/ ATAPI Controller

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