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HS-54C138RH
August 2000
File Number
3037.3
Radiation Hardened 3-Line to 8-Line
Decoder/Demultiplexer
The Intersil HS-54C138RH is a radiation hardened 3- to
8-line decoder fabricated using a radiation hardened
EPI-CMOS process. It features low power consumption,
high noise immunity, and high speed. Also featured are pin
and function compatibility with the 54LS138 industry
standard part. The HS-54C138RH is ideally suited for high
speed memory chip select address decoding. It is intended
for use with the Intersil HS-80C85RH radiation hardened
microprocessor, but it can also be utilized as a demultiplexer
in any low power rad-hard application.
The HS-54C138RH contains a one of eight binary decoder.
A three bit binary input is used to select and activate each of
the eight outputs, provided the three chip enable inputs are
also present (see truth table).
The HS-54C138RH has an on-chip enable gate. The active
high (G1) and both active low (G2A, G2B) inputs are Anded
together to provide a single enable input to the device. The
use of both active high and active low inputs minimizes the
need for external gates when expanding a system.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95825. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Features
• Electrically Screened to SMD # 5962-95825
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened EPI-CMOS
- Total Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 10
5
RAD(Si)
- Latch-Up Immune . . . . . . . . . . . . . . >1 x 10
12
RAD(Si)/s
• Multiple Input Enable for Easy Expansion
• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . .+5V
• Outputs Active Low
• Low Standby Power . . . . . . . . . . . . . . .0.5mW Max at +5V
• High Noise Immunity
• Equivalent to Sandia SA2995
• Bus Compatible with Intersil Rad-Hard 80C85RH
• Full Military Temperature Range . . . . . . . -55
o
C to 125
o
C
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
A 1
B 2
C 3
G2A 4
G2B 5
G1 6
16 VDD
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
Ordering Information
ORDERING NUMBER
5962R9582501QEC
5962R9582501QXC
5962R9582501V9A
5962R9582501VEC
5962R9582501VXC
INTERNAL
MKT. NUMBER
HS1-54C138RH-8
HS9-54C138RH-8
HS0-54C138RH-Q
HS1-54C138RH-Q
HS9-54C138RH-Q
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
25
-55 to 125
-55 to 125
A
B
C
G2A
G2B
G1
Y7
GND
Y7 7
GND 8
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HS-54C138RH
Typical Applications
Typical applications include systems which require multiple
input/output ports and memories. When the HS-54C138RH
is enabled one of the eight outputs will go low. This output
can be used to select a particular device or a group of
devices. The HS-54C138RH can also be cascaded to
provide an enabling scheme for larger systems and allow
one decoder to control eight other decoders as in Figure 1.
Figure 2 shows a configuration that can be used to enable
multiple I/O ports or memory devices. Up to 24 memory
devices or I/O ports can be controlled using this circuit.
For demultiplexer operation, one of the three enable inputs
is used as the data input while the other two inputs are
enable. The transmitted data is distributed to the proper
output as determined by the 3-line select inputs. See Figure
3.
SELECT A
SELECT B
ENABLE
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
TO OTHER
DEVICES
“1” “0”
ENABLE
“1” “0”
ENABLE
“1” “0”
ENABLE
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
FIGURE 1.
EN
EN
EN A4
A3
A2 A1 A0
G1 G2B G2A
C
B
A
G1 G2B G2A
C
B
A
G1 G2B G2A
C
B
A
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
PORT NUMBERS OR CHIP SELECTS
FIGURE 2.
2
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