Si53306
1 : 4 L
O W
-J
ITTER
U
N I V E R S A L
B
U F F E R
/ L
E V E L
T
R A N S L A T O R
Features
4 differential or 8 LVCMOS outputs
Ultra-low additive jitter: 45 fs rms
Wide frequency range: 1 to 725 MHz
Any-format input with pin selectable
output formats: LVPECL, low power
LVPECL, LVDS, CML, HCSL,
LVCMOS
Synchronous output enable
Independent V
DD
and V
DDO
:
1.8/2.5/3.3 V
1.2/1.5 V LVCMOS output support
Selectable LVCMOS drive strength to
tailor jitter and EMI performance
Small size: 16-QFN (3 mm x 3 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Applications
OE
Q0
15
The Si53306 is an ultra low jitter four output differential buffer with pin-selectable
output clock signal format. The Si53306 utilizes Silicon Laboratories' advanced
CMOS technology to fanout clocks from 1 to 725 MHz with guaranteed low
additive jitter, low skew, and low propagation delay variability. The Si53306
features minimal cross-talk and provides superior supply noise rejection,
simplifying low jitter clock distribution in noisy environments. Independent core
and output bank supply pins provide integrated level translation without the need
for external circuitry.
Q0
14
Description
V
DD
CLK
CLK
GND
SFOUT0
13
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Ordering Information:
See page 24.
Pin Assignments
16
1
2
3
4
5
12
Q1
Q1
Q2
Q2
GND
PAD
11
10
9
Functional Block Diagram
VDDO
SFOUT[1:0]
VDD
Power
Supply
Filtering
OE
Q0
Q0
Q1
CLK
CLK
Q1
Q2
Q2
Q3
Q3
6
7
Patents pending
Rev. 1.0 2/15
Copyright © 2015 by Silicon Laboratories
SFOUT1
Si53306
V
DDO
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
Q3
Q3
8
Si53306
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5. Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6. Power Supply (V
DD
and V
DDO
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.8. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.9. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.10. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3. Pin Description: 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1. Si53306 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2
Rev. 1.0
Si53306
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
T
A
V
DD
LVDS, CML
Test Condition
Min
–40
1.71
2.38
2.97
LVPECL, low power LVPECL,
LVCMOS
HCSL
Output Buffer Supply
Voltage*
V
DDOX
LVDS, CML, LVCMOS
2.38
2.97
2.97
1.71
2.38
2.97
LVPECL, low power LVPECL
2.38
2.97
HCSL
2.97
Typ
—
1.8
2.5
3.3
2.5
3.3
3.3
1.8
2.5
3.3
2.5
3.3
3.3
Max
85
1.89
2.63
3.63
2.63
3.63
3.63
1.89
2.63
3.63
2.63
3.63
3.63
Unit
°C
V
V
V
V
V
V
V
V
V
V
V
V
*Note:
Core supply V
DD
and output buffer supplies V
DDO
are independent. LVCMOS clock input is not supported for
V
DD
=
1.8V but is supported for LVCMOS clock output for
V
DDOX
= 1.8V. LVCMOS outputs at 1.5V and 1.2V can be
supported via a simple resistor divider network. See “2.7.1. LVCMOS Output Termination To Support 1.5V and 1.2V”
Table 2. Input Clock Specifications
(V
DD
=1.8 V
5%, 2.5 V
5%, or 3.3 V
10%, T
A
=–40 to 85 °C)
Parameter
Differential Input Common
Mode Voltage
Differential Input Swing
(peak-to-peak)
LVCMOS Input High Volt-
age
LVCMOS Input Low Volt-
age
Input Capacitance
Symbol
V
CM
V
IN
V
IH
V
IL
C
IN
V
DD
= 2.5 V
5%, 3.3 V
10%
V
DD
= 2.5 V
5%, 3.3 V
10%
CLK pins with respect to GND
Test Condition
V
DD
= 2.5 V
5%, 3.3 V
10%
Min
0.05
0.2
V
DD
x 0.7
—
—
Typ
—
—
—
—
5
Max
—
2.2
—
V
DD
x
0.3
—
Unit
V
V
V
V
pF
Rev. 1.0
3
Si53306
Table 3. DC Common Characteristics
(V
DD
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Supply Current
Output Buffer
Supply Current
(Per Clock Output)
@100 MHz (diff)
@200 MHz (CMOS)
Symbol
I
DD
I
DDOX
Test Condition
Min
—
Typ
55
35
35
20
40
35
5
10
20
VDD/2
—
0.5 x
VDD
—
25
25
Max
100
—
—
—
—
—
—
—
—
—
—
0.55 x
VDD
0.2 x
VDD
—
—
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
k
k
LVPECL (3.3 V)
Low Power LVPECL (3.3 V)*
LVDS (3.3 V)
CML (3.3 V)
HCSL, 100 MHz, 2 pF load (3.3 V)
CMOS (1.8 V, SFOUT = Open/0),
per output, C
L
= 5 pF, 200 MHz
CMOS (2.5 V, SFOUT = Open/0),
per output, C
L
= 5 pF, 200 MHz
CMOS (3.3 V, SFOUT = 0/1),
per output, C
L
= 5 pF, 200 MHz
—
—
—
—
—
—
—
—
—
0.8 x
VDD
0.45 x
VDD
—
—
—
Input Clock Voltage
Reference
Input High Voltage
Input Mid Voltage
Input Low Voltage
Internal Pull-down
Resistor
Internal Pull-up
Resistor
V
REF
V
IH
V
IM
V
IL
R
DOWN
R
UP
V
REF
pin
I
REF
= +/-500
A
SFOUTx, OE
SFOUTx
3-level input pins
SFOUTx, OE
SFOUTx
SFOUTx, OE
*Note:
Low-power LVPECL mode supports an output termination scheme that will reduce overall system power.
4
Rev. 1.0
Si53306
Table 4. Output Characteristics (LVPECL)
(V
DDOX
= 2.5 V ± 5%, or 3.3 V ± 10%,T
A
= –40 to 85 °C)
Parameter
Output DC Common Mode
Voltage
Single-Ended
Output Swing*
Symbol
V
COM
V
SE
Test Condition
Min
V
DDOX
– 1.595
0.55
Typ
—
0.80
Max
V
DDOX
– 1.245
1.050
Unit
V
V
*Note:
Unused outputs can be left floating. Do not short unused outputs to ground.
Table 5. Output Characteristics (Low Power LVPECL)
(V
DDOX
= 2.5 V ± 5%, or 3.3 V ± 10%,T
A
= –40 to 85 °C)
Parameter
Output DC Common
Mode Voltage
Single-Ended
Output Swing
Symbol
V
COM
V
SE
Test Condition
R
L
= 100
across
Qn and Qn
R
L
= 100
across
Qn and Qn
Min
V
DDOX
– 1.895
0.25
Typ
Max
V
DDOX
– 1.275
Unit
V
V
0.60
0.85
Table 6. Output Characteristics—CML
(V
DDOX
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Symbol
V
SE
Test Condition
Terminated as shown in Figure 7
(CML termination).
Min
300
Typ
400
Max
550
Unit
mV
Table 7. Output Characteristics—LVDS
(V
DDOX
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Output Common
Mode Voltage
(V
DDO
= 2.5 V or
3.3V)
Output Common
Mode Voltage
(V
DDO
= 1.8 V)
Symbol
V
SE
V
COM1
Test Condition
R
L
= 100
Ω
across Q
N
and Q
N
V
DDOX
= 2.38 to 2.63 V, 2.97 to
3.63 V, R
L
= 100
Ω
across Q
N
and Q
N
V
DDOX
= 1.71 to 1.89 V,
R
L
= 100
Ω
across Q
N
and Q
N
Min
247
1.10
Typ
—
1.25
Max
490
1.35
Unit
mV
V
V
COM2
0.85
0.97
1.25
V
Rev. 1.0
5
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