®
November 2002
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1-888-
CA3318
CMOS Video Speed,
8-Bit, Flash A/D Converter
Features
• CMOS Low Power with SOS Speed (Typ) . . . . . . . .150mW
• Parallel Conversion Technique
• 15MHz Sampling Rate (Conversion Time) . . . . . . . 67ns
• 8-Bit Latched Three-State Output with Overflow Bit
• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .
±1
LSB
• Single Supply Voltage . . . . . . . . . . . . . . . . . . 4V to 7.5V
• 2 Units in Series Allow 9-Bit Output
• 2 Units in Parallel Allow 30MHz Sampling Rate
Description
The CA3318 is a CMOS parallel (FLASH) analog-to-digital
converter designed for applications demanding both low
power consumption and high speed digitization.
The CA3318 operates over a wide full scale input voltage
range of 4V up to 7.5V with maximum power consumption
depending upon the clock frequency selected. When
operated from a 5V supply at a clock frequency of 15MHz,
the typical power consumption of the CA3318 is 150mW.
The intrinsic high conversion rate makes the CA3318 ideally
suited for digitizing high speed signals. The overflow bit
makes possible the connection of two or more CA3318s in
series to increase the resolution of the conversion system. A
series connection of two CA3318s may be used to produce a
9-bit high speed converter. Operation of two CA3318s in
parallel doubles the conversion speed (i.e., increases the
sampling rate from 15MHz to 30MHz).
256 paralleled auto balanced voltage comparators measure
the input voltage with respect to a known reference to
produce the parallel bit outputs in the CA3318.
255 comparators are required to quantize all input voltage
levels in this 8-bit converter, and the additional comparator is
required for the overflow bit.
Applications
•
•
•
•
•
•
•
•
•
•
TV Video Digitizing (Industrial/Security/Broadcast)
High Speed A/D Conversion
Ultrasound Signature Analysis
Transient Signal Analysis
High Energy Physics Research
General-Purpose Hybrid ADCs
Optical Character Recognition
Radar Pulse Analysis
Motion Signature Analysis
µP
Data Acquisition Systems
Part Number Information
PART NUMBER LINEARITY (INL, DNL)
CA3318CE
CA3318CM
CA3318CD
±1.5
LSB
±1.5
LSB
±1.5
LSB
SAMPLING RATE
15MHz (67ns)
15MHz (67ns)
15MHz (67ns)
TEMP. RANGE (
o
C)
-40 to 85
-40 to 85
-40 to 85
PACKAGE
24 Ld PDIP
24 Ld SOIC
24 Ld SBDIP
PKG. NO.
E24.6
M24.3
D24.6
Pinout
CA3318
(PDIP, SBDIP, SOIC)
TOP VIEW
(LSB) B1 1
B2 2
B3 3
B4 4
B5 5
B6 6
B7 7
(MSB) B8 8
OVERFLOW 9
1
/ R 10
4
24 V
AA
+ (ANA. SUP.)
23
3
/
4
R
22 V
REF
+
21 V
IN
20 p
19 PHASE
18 CLK
17 V
AA
- (ANA. GND)
16 V
IN
15 V
REF
-
14 CE1
13 CE2
(DIG. GND) V
SS
11
(DIG. SUP.) V
DD
12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
FN3103.3
1
CA3318
Functional Block Diagram
V
AA
+
24
V
IN
21
V
REF
+
1
/
2
R
22
CAB
# 256
R = 2Ω
LATCH
256
LATCH
256
ENCODER
LOGIC
ARRAY
D
Q
D
Q
COUNT
256
ANALOG
SUPPLY
φ
2
φ
1
φ
1
φ
1
φ
1
φ
2
φ
1
V
DD
DIGITAL
SUPPLY
12
THREE-
STATE
OUTPUT
REGISTER DRIVERS OVER-
FLOW
D Q
CLK
BIT 8
(MSB)
D Q
CLK
BIT 7
D Q
CLK
7
8
9
3
/ REF
4
R
D
CAB
# 193
LATCH
LATCH
Q
D
Q
COUNT
193
23
= 7Ω
R
BIT 6
D Q
6
COUNT
129
1
/ REF
2
R
CAB
# 129
R
CLK
BIT 5
D Q
5
D
Q
D
Q
20
= 30Ω
LATCH
LATCH
CLK
BIT 4
1
/ REF
4
R
D
CAB
# 65
R
LATCH
LATCH
Q
D
Q
COUNT
65
D Q
CLK
4
10
= 4Ω
V
IN
16
R
V
REF
-
15
BIT 3
D Q
CLK
COUNT
1
D Q
CLK
LATCH
1
LATCH
11
D Q
BIT 1
(LSB)
1
BIT 2
2
3
≅
2K
1
/ R
2
D
CAB
(NOTE 1)
COMPARATOR #1
Q
D
Q
≅
50K
CLOCK
18
PHASE
19
V
AA
-
17
φ
1 (AUTO BALANCE)
CLK
φ
2 (SAMPLE UNKNOWN)
CE1
14
ANALOG
GND
CE2
NOTE:
1. Cascaded Auto Balance (CAB).
DIGITAL
GND
13
V
SS
11
2
CA3318
Absolute Maximum Ratings
DC Supply Voltage Range (V
DD
or V
AA
+) . . . . . . . . . . -0.5V to +8V
(Referenced to V
SS
or V
AA
- Terminal, Whichever is More Negative)
Input Voltage Range
CE2 and CE1 . . . . . . . . . . . . . . . . . . . . V
AA
- -0.5V to V
DD
+ 0.5V
Clock, Phase, V
REF
-,
1
/
2
Ref . . . . . . . V
AA
- -0.5V to V
AA
+ + 0.5V
Clock, Phase, V
REF
-,
1
/
4
Ref . . . . . . . . V
SS
- -0.5V to V
DD
+ 0.5V
V
IN
,
3
/
4
REF, V
REF
+ . . . . . . . . . . . . . .V
AA
- -0.5V to V
AA
- + 7.5V
Output Voltage Range, . . . . . . . . . . . . . . . V
SS
- 0.5V to V
DD
+ 0.5V
Bits 1-8, Overflow (Outputs Off)
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20mA
Clock, Phase, CE1, CE2, V
IN
, Bits 1-8, Overflow
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
SBDIP Package. . . . . . . . . . . . . . . . . . . .
60
22
PDIP Package . . . . . . . . . . . . . . . . . . . . .
60
N/A
SOIC Package. . . . . . . . . . . . . . . . . . . . .
75
N/A
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 265
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Operating Voltage Range (V
DD
or V
AA
+) . . 4V (Min) to 7.5V (Max)
Recommended V
AA
+ Operating Range. . . . . . . . . . . . . . . V
DD
±1V
Recommended V
AA
- Operating Range . . . . . . . . . . . . . . . V
SS
±1V
Operating Temperature Range (T
A
). . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error
Differential Linearity Error
Offset Error, Unadjusted
Gain Error Unadjusted
DYNAMIC CHARACTERISTICS
Maximum Input Bandwidth
Maximum Conversion Speed
Signal to Noise Ratio (SNR)
RMSSignal
=
--------------------------------
RMSNoise
Signal to Noise Ratio (SINAD)
RMSSignal
=
-----------------------------------------------------------
-
RMSNoise+Distortion
Total Harmonic Distortion, THD
Effective Number of Bits (ENOB)
Differential Gain Error
Differential Phase Error
ANALOG INPUTS
At 25
o
C, V
AA
+ = V
DD
= 5V, V
REF
+ = 6.4V, V
REF
- = V
AA
- = V
SS
, CLK = 15MHz,
All Reference Points Adjusted, Unless Otherwise Specified
TEST CONDITIONS
MIN
8
-
-
V
IN
= V
REF
- +
1
/
2
LSB
V
IN
= V
REF
+ -
1
/
2
LSB
(Note 1) CA3318
CLK = Square Wave
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 4MHz
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 4MHz
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 4MHz
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 4MHz
Unadjusted
Unadjusted
Notes 2, 4
V
IN
= 5V, V
REF
+ = 5V
-0.5
-1.5
TYP
-
-
-
4.5
0
MAX
-
±
1.5
+1, -0.8
6.4
1.5
UNITS
Bits
LSB
LSB
LSB
LSB
2.5
15
-
-
-
-
-
-
-
-
-
-
4
-
-
270
5.0
17
47
43
45
35
-46
-36
7.2
5.5
2
1
-
30
-
500
-
-
-
-
-
-
-
-
-
-
-
-
7
-
3.5
800
MHz
MSPS
dB
dB
dB
dB
dBc
dBc
Bits
Bits
%
%
V
pF
mA
Ω
Full Scale Range, V
IN
and (V
REF
+) - (V
REF
-)
Input Capacitance, V
IN
Input Current, V
IN
, (See Text)
REFERENCE INPUTS
Ladder Impedance
3
CA3318
Electrical Specifications
PARAMETER
DIGITAL INPUTS
Low Level Input Voltage, V
OL
CE1, CE2
Phase, CLK
High Level Input Voltage, V
IN
CE1, CE2
Phase, CLK
Input Leakage Current, I
I
(Except CLK Input)
Input Capacitance, C
I
DIGITAL OUTPUTS
Output Low (Sink) Current
Output High (Source) Current
Three-State Output Off-State Leakage Current, I
OZ
Output Capacitance, C
O
TIMING CHARACTERISTICS
Auto Balance Time (
φ
1)
Sample Time (
φ
2)
Aperture Delay
Aperture Jitter
Data Valid Time, t
D
Data Hold Time, t
H
Output Enable Time, t
EN
Output Disable Time, t
DIS
POWER SUPPLY CHARACTERISTICS
Device Current (I
DD
+ I
A
) (Excludes I
REF
)
Continuous Conversion (Note 4)
Auto Balance (
φ
1)
-
-
30
30
60
60
mA
mA
Note 4
Note 4
Note 4
33
25
-
-
-
25
-
-
-
-
15
100
50
40
18
18
V
O
= 0.4V
V
O
= 4.5V
4
-4
-
-
10
-6
±0.2
4
-
-
±5
-
mA
mA
µA
pF
ns
ns
ns
ps
ns
ns
ns
ns
Note 4
Note 4
Note 4
Note 4
Note 3
-
-
0.7V
DD
0.7V
AA
-
-
-
-
-
-
±0.2
3
0.2V
DD
0.2V
AA
-
-
±5
-
V
V
V
V
µA
pF
At 25
o
C, V
AA
+ = V
DD
= 5V, V
REF
+ = 6.4V, V
REF
- = V
AA
- = V
SS
, CLK = 15MHz,
All Reference Points Adjusted, Unless Otherwise Specified
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
∞
500
-
-
65
-
-
-
NOTES:
1. A full scale sine wave input of greater than f
CLOCK
/2 or the specified input bandwidth (whichever is less) may cause an erroneous code.
The -3dB bandwidth for frequency response purposes is greater than 30MHz.
2. V
IN
(Full Scale) or V
REF
+ should not exceed V
AA
+ + 1.5V for accuracy.
3. The clock input is a CMOS inverter with a 50kΩ feedback resistor and may be AC coupled with 1V
P-P
minimum source.
4. Parameter not tested, but guaranteed by design or characterization.
Timing Waveforms
DECODED DATA IS SHIFTED
TO OUTPUT REGISTERS
COMPARATOR DATA IS LATCHED
CLOCK (PIN 18)
IF PHASE (PIN 19)
IS LOW
φ
2
φ
1
φ
2
φ
1
φ
2
CLOCK IF
PHASE IS HIGH
SAMPLE
N
AUTO
BALANCE
SAMPLE
N+1
AUTO
BALANCE
t
D
t
H
SAMPLE
N+2
DATA
N-2
DATA
N-1
DATA
N
FIGURE 1. INPUT TO OUTPUT TIMING DIAGRAM
4
CA3318
Timing Waveforms
(Continued)
CE1
CE2
t
DIS
t
EN
t
DIS
BITS 1 - 8
DATA
HIGH
IMPEDANCE
OF
DATA
HIGH
IMPEDANCE
DATA
HIGH
IMPEDANCE
t
EN
DATA
FIGURE 2. OUTPUT ENABLE TIMING DIAGRAM
AUTO
BALANCE
CLOCK
NO MAX
LIMIT
SAMPLE
N
25ns
MIN
AUTO
BALANCE
SAMPLE
N+1
33ns
MIN
25ns
MIN
50ns
MIN
DATA
FIGURE 3A. STANDBY IN INDEFINITE AUTO BALANCE (SHOWN WITH PHASE = LOW)
CLOCK
SAMPLE
N
500ns
MAX
AUTO
BALANCE
SAMPLE
N+1
25ns
MIN
AUTO
BALANCE
SAMPLE
N+2
33ns
MIN
50ns
TYP
DATA
DATA
N-1
DATA
N
FIGURE 3B. STANDBY IN SAMPLE (SHOWN WITH PHASE = LOW)
FIGURE 3. PULSE MODE OPERATION
5
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