SG564568FG8NWUU
May 28, 2008
Ordering Information
Part Numbers
SG564568FG8NWDB
Description
256Mx64 (2GB), DDR2, 200-pin SO-DIMM, Unbuffered,
Non-ECC, 128Mx8 Based, DDR2-400-333, 30.00mm,
22Ω DQ termination, Green Module (RoHS Compliant).
256Mx64 (2GB), DDR2, 200-pin SO-DIMM, Unbuffered,
Non-ECC, 128Mx8 Based, DDR2-533-444, 30.00mm,
22Ω DQ termination, Green Module (RoHS Compliant).
256Mx64 (2GB), DDR2, 200-pin SO-DIMM, Unbuffered,
Non-ECC, 128Mx8 Based, DDR2-667-555, 30.00mm,
22Ω DQ termination, Green Module (RoHS Compliant).
256Mx64 (2GB), DDR2, 200-pin SO-DIMM, Unbuffered,
Non-ECC, 128Mx8 Based, DDR2-800-555, 30.00mm,
22Ω DQ termination, Green Module (RoHS Compliant).
256Mx64 (2GB), DDR2, 200-pin SO-DIMM, Unbuffered,
Non-ECC, 128Mx8 Based, DDR2-800-666, 30.00mm,
22Ω DQ termination, Green Module (RoHS Compliant).
Module Speed
PC2-3200 @ CL 3.0
SG564568FG8NWDG
PC2-4200 @ CL 4.0
SG564568FG8NWIL
PC2-5300 @ CL 5.0
SG564568FG8NWIR
PC2-6400 @ CL 5.0
SG564568FG8NWKF
PC2-6400 @ CL 6.0
(All specifications of this module are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SG564568FG8NWUU
May 28, 2008
Revision History
• May 28, 2008
Added SG564568FG8NWIR & SG564568FG8NWKF to the Ordering Information on page 1.
• January 22, 2007
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SG564568FG8NWUU
May 28, 2008
2GByte (256Mx64) DDR2 SDRAM Module - 128Mx8 Based
200-pin SO-DIMM, Unbuffered, Non-ECC
Features
• Standard
• Configuration
• Cycle Time
:
:
:
JEDEC
Non-ECC
5.0ns (DDR2-400)
3.75ns (DDR2-533)
3.0ns (DDR2-667)
2.5ns (DDR2-800)
3.0, 4.0 (-DB/DG)
4.0, 5.0 (-IL/IR)
5.0, 6.0 (-KF)
0, 1.0, 2.0, 3.0 & 4.0
Read (CAS#) Latency - 1
4, 8
•
•
•
•
•
•
•
•
•
•
•
Burst Type
:
Sequential/Interleave
Module Ranks
:
2 Ranks of x8 devices
No. of Devices
:
16
No. of Internal
Banks per SDRAM :
8
Operating Voltage :
1.8V
Refresh
:
8K/64ms
Device Physicals :
FBGA
Lead Finish
:
Gold
Length x Height
:
67.60mm x 30.00mm
No. of sides
:
Double-sided
Mating Connector (Examples)
Horizontal
:
AMP - 1473150-4
• CAS# Latency
:
• Posted CAS#/Additive
Latency (AL)
:
• Write Latency (WL)
:
• Burst Length
:
DDR2 200-pin SO-DIMM Pin List
Pin Pin
No. Name
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
Pin Pin
No. Name
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
CK0
CK0#
V
SS
DQ14
DQ15
V
SS
Pin Pin
No. Name
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12
Pin Pin
No. Name
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS3#
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
A15 (NC)
A14 (NC)
V
DD
A11
Pin Pin
No. Name
101 A1
103 V
DD
105 A10/AP
107 BA0
109 WE#
111
V
DD
Pin Pin
No. Name
102 A0
104 V
DD
106 BA1
108 RAS#
110 CS0#
112 V
DD
114 ODT0
116 A13
118 V
DD
120 NC
122 V
SS
124 DQ36
126 DQ37
128 V
SS
130 DM4
132 V
SS
134 DQ38
136 DQ39
138 V
SS
140 DQ44
Pin Pin
No. Name
151 DQ42
153 DQ43
155 V
SS
157 DQ48
159 DQ49
161 V
SS
163 NC
165 V
SS
167 DQS6#
169 DQS6
171 V
SS
173 DQ50
175 DQ51
177 V
SS
179 DQ56
181 DQ57
183 V
SS
185 DM7
187 V
SS
189 DQ58
Pin Pin
No. Name
152 DQ46
154 DQ47
156 V
SS
158 DQ52
160 DQ53
162 V
SS
164 CK1
166 CK1#
168 V
SS
170 DM6
172 V
SS
174 DQ54
176 DQ55
178 V
SS
180 DQ60
182 DQ61
184 V
SS
186 DQS7#
188 DQS7
190 V
SS
113 CAS#
115 CS1#
117 V
DD
119 ODT1
121 V
SS
123 DQ32
125 DQ33
127 V
SS
129 DQS4#
131 DQS4
133 V
SS
135 DQ34
137 DQ35
139 V
SS
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SG564568FG8NWUU
May 28, 2008
DDR2 200-pin SO-DIMM Pin List (Contd.)
Pin Pin
No. Name
41
43
45
47
49
V
SS
DQ16
DQ17
V
SS
DQS2#
Pin Pin
No. Name
42
44
46
48
50
V
SS
DQ20
DQ21
V
SS
NC
Pin Pin
No. Name
91
93
95
97
99
A9
A8
V
DD
A5
A3
Pin Pin
No. Name
92
94
96
98
A7
A6
V
DD
A4
Pin Pin
No. Name
141 DQ40
143 DQ41
145 V
SS
147 DM5
149 V
SS
Pin Pin
No. Name
142 DQ45
144 V
SS
146 DQS5#
148 DQS5
150 V
SS
Pin Pin
No. Name
191 DQ59
193 V
SS
195 SDA
197 SCL
199 V
DDSPD
Pin Pin
No. Name
192 DQ62
194 DQ63
196 V
SS
198 SA0
200 SA1
100 A2
Pin Description Table
Symbol
CK0, CK1
Type
SSTL_18
Polarity
Positive Edge
Function
Positive line of the differential pair of system clock inputs. (All DDR2 SDRAM address and
control inputs are sampled on the rising edge of their associated clocks. Output data is ref-
erenced at the crossings of the clocks.)
Negative line of the differential pair of system clock inputs.
On-Die Termination: ODT when high enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, and
DM. The ODT input will be ignored if disabled in Extended Mode Register (EMRS).
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored but previous operations con-
tinue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operations to be executed by the SDRAM.
Bank Address define to which bank an Activate, Read, Write or Precharge command is
being applied. Bank address also determines if the Mode Register or Extended Mode
Register is to be accessed during a MRS or EMRS cycle.
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, A10/AP is used
to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high,
autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to con-
trol which bank(s) to precharge. If AP is high, all banks will be precharged regardless of
the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to pre-
charge. The address inputs also provide the op-code during Mode Register Set com-
mands.
CK0#, CK1#
ODT0, ODT1
SSTL_18
SSTL_18
Negative Edge
Active High
CKE0, CKE1
SSTL_18
Active High
CS0#, CS1#
SSTL_18
Active Low
RAS#, CAS#,
WE#
BA0~BA2
SSTL_18
SSTL_18
Active Low
-
A0~A9, A10/AP,
A11~A13
SSTL_18
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SG564568FG8NWUU
May 28, 2008
Pin Description Table (Contd.)
Symbol
DQ0~DQ63
DQS0~DQS7
DQS0#~DQS7#
DM0~DM7
Type
SSTL_18
SSTL_18
SSTL_18
SSTL_18
Polarity
-
Positive Edge
Negative Edge
Active High
Function
Data Input/Output pins.
SDRAM differential data strobe for input and output data.
SDRAM differential data strobe for input and output data.
DM is an input mask signal for write data. Input data is masked when DM is sampled high
coincident with that input data during a write access. DM is sampled on both edges of
DQS. Although DM pins are input only, the DM loading matches the DQ/DQS loading.
Slave Address Select for EEPROM. These pins are used to configure the presence-detect
device.
Serial Bus Data Line for EEPROM. SDA is a bidirectional pin used to transfer addresses
and data into and out of the presence-detect portion of the module. A resistor must be
connected from the SDA bus line to V
DDSPD
to act as pull up on the system board.
Serial Bus Clock for EEPROM. SCL is used to synchronize the presence-detect data
transfer to and from the module. A resistor may be connected from the SCL bus line to
V
DDSPD
to act as pull up on the system board.
SDRAM positive power supply. 1.8V±0.1V
Power supply return (ground).
SDRAM I/O reference supply.
Serial EEPROM positive power supply (wired to a separate power pin at the connector
which supports operation from 1.7V to 3.6V).
No Connect.
SA0~SA1
SDA
LVTTL
LVTTL
-
-
SCL
LVTTL
-
V
DD
V
SS
V
REF
V
DDSPD
NC
Supply
Supply
Supply
Supply
-
-
-
-
-
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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