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8 -I
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®
HS-80C85RH
August 2000
File Number
3036.3
Radiation Hardened 8-Bit CMOS
Microprocessor
The HS-80C85RH is an 8-bit CMOS microprocessor
fabricated using the Intersil radiation hardened self-aligned
junction isolated (SAJI) silicon gate technology. Latch-up
free operation is achieved by the use of epitaxial starting
material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-80C85RH is a functional logic emulation of the
HMOS 8085 and its instruction set is 100% software
compatible with the HMOS device. The HS80C85RH is
designed for operation with a single 5 volt power supply. Its
high level of integration allows the construction of a radiation
hardened microcomputer system with as few as three ICs
(HS-80C85RH CPU, HS83C55RH ROM I/O, and the
HS-81C55/56RH RAM I/O.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95824. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Features
• Electrically Screened to SMD # 5962-95824
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed . . . . . . . . . . . 1 x 10
5
RAD(Si)
- Transient Upset . . . . . . . . . . . . . . . . >1 x 10
8
RAD(Si)/s
- Latch-up Free . . . . . . . . . . . . . . . . . >1 x 10
12
RAD(Si)/s
• Low Standby Current . . . . . . . . . . . . . . . . . . . . 500µA Max
• Low Operating Current. . . . . . . . . . 5.0mA/MHz (X
1
Input)
• Electrically Equivalent to Sandia SA 3000
• 100% Software Compatible with INTEL 8085
• Operation from DC to 2MHz, Post Radiation
• Single 5V Power Supply
• On-Chip Clock Generator and System Controller
• Four Vectored Interrupt Inputs
• Completely Static Design
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range. . . . . . . . . . . -55
o
C to 125
o
C
Ordering Information
ORDERING NUMBER
5962R9582401QQC
5962R9582401QXC
5962R9582401VQC
5962R9582401VXC
HS9-80C85RH/Proto
INTERNAL
MKT. NUMBER
HS1-80C85RH-8
HS9-80C85RH-8
HS1-80C85RH-Q
HS9-80C85RH-Q
HS9-80C85RH/Proto
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HS-80C85RH
Pinouts
40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835, CDIP2-T40
TOP VIEW
X1 1
X2 2
RESET OUT 3
SOD 4
SID 5
TRAP 6
RST 7.5 7
RST 6.5 8
RST 5.5 9
INTR 10
INTA 11
AD0 12
AD1 13
AD2 14
AD3 15
AD4 16
AD5 17
AD6 18
AD7 19
GND 20
40 VDD
39 HOLD
38 HLDA
37 CLOCK OUT
36 RESET IN
35 READY
34 IO/ M
33 S1
32 RD
31 WR
30 ALE
29 S0
28 A15
27 A14
26 A13
25 A12
24 A11
23 A10
22 A9
21 A8
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) INTERSIL OUTLINE K42.A
TOP VIEW
X1
X2
RESET
OUT
SOD
SID
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
INTA
AD0
AD1
AD2
AD3
AD4
NC
NC
AD5
AD6
AD7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
HOLD
HLDA
CLOCK
OUT
RESET
IN
READY
IO/ M
S1
RD
WR
ALE
S0
A15
A14
A13
A12
A11
A10
A9
A8
GND
Functional Diagram
INTR
INTA
RST
5.5
RST
6.5
RST
7.5 TRAP
SID
SOD
INTERRUPT CONTROL
SERIAL I/O CONTROL
8-BIT
INTERNAL DATA BUS
ACCUMU-
LATOR (8)
TEMP REG
(8)
FLAG (5)
FLIP FLOPS
INSTRUCTION
REGISTER (8)
B REG (8)
D REG (8)
H REG (8)
C REG (8)
REGISTER ARRAY
DATA ADDRESS
BUFFER (8)
AD1-AD0
ADDRESS
BUS
E REG (8)
L REG (8)
ARITHMETIC
LOGIC
UNIT
(ALU) (8)
POWER
SUPPLY
X1
X2
VDD
GND
CLK
GEN
INSTRUCTION
DECODER
AND MACHINE
CYCLE
ENCODING
STACK POINTER (16)
PROGRAM COUNTER (16)
INCREMENTER
DECREMENTER
ADDRESS LATCH (16)
TIMING AND CONTROL
CONTROL
STATUS
DMA
RESET
ADDRESS
BUFFER (8)
READY
CLK
OUT
RD
WR
ALE
S0
S1
IO/M
HLDA
HOLD
RESET
IN
RESET
OUT
A15-A8
ADDRESS
BUS
2
HS-80C85RH
Pin Description
SYMBOL
A8 - A15
AD0-7
PIN
NUMBER
21-28
12-19
TYPE
O
I/O
DESCRIPTION
Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,
three-stated during Hold and Halt modes and during RESET.
Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the bus
during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second
and third clock cycles.
Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the address
to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guarantee setup and
hold times for the address information. The falling edge of ALE can also be used to strobe the status
information. ALE is never three-stated.
Machine Cycle Status:
IO/M
0
0
1
1
0
1
1
T
T
T
S1
0
1
0
1
1
1
1
0
X
X
S0
1
0
1
0
1
1
1
0
X
X
STATUS
Memory write
Memory write
I/O write
I/O read
Opcode fetch
Opcode fetch
Interrupt acknowledge
Halt
Hold
Reset
ALE
32
O
S0, S1, and
IO/M
31, 35,
and 36
O
T = three-State (high impedance)
X = Unspecified
S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of a machine
cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of
these lines.
RD
WR
34
33
O
O
Read Control: A low level on RD indicates the selected memory or I/O device is to be read and that the
Data Bus is available for the data transfer, three-stated during Hold and Halt modes and during RESET.
Write Control: A low level on WR indicates the data on the Data Bus is to be written into the selected
memory or I/O location. Data is set up at the trailing edge of WR, three-stated during Hold and Halt modes
and during RESET.
Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready
to send or receive data. If READY is low, the CPU will wait an integral number of clock cycles for READY
to go high before completing the read or write cycle. READY must conform to specified setup and hold
times.
Hold: Indicates that another master is requesting the use of the address and data buses. The CPU, upon
receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus
transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is
removed. When the HOLD is acknowledged, the Address, Data Bus, RD, WR, and IO/M lines are
3-stated.
Hold Acknowledge: Indicates that the CPU has received the HOLD request and that it will relinquish the
bus in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the bus
one half clock cycle after HLDA goes low.
Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to the last
clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will
be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL
instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by
software. It is disabled by Reset and immediately after an interrupt is accepted.
READY
35
I
HOLD
39
I
HLDA
38
O
INTR
10
I
3
HS-80C85RH
Pin Description
SYMBOL
INTA
RST 5.5
RST 6.5
RST 7.5
TRAP
(Continued)
TYPE
O
I
DESCRIPTION
Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruction cycle
after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some other interrupt port.
Restart Interrupts: These three inputs have the same timing as INTR except they cause an internal
RESTART to be automatically inserted.
The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher priority than
INTR. In addition, they may be individually masked out using the SIM instruction.
Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as INTR or
RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.
(See Table 6.)
Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops. The data
and address buses and the control lines are three-stated during RESET and because of the
asynchronous nature of RESET the processor’s internal registers and flags may be altered by RESET
with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C network
for power-on RESET delay (see Figure 1). Upon power-up, RESET IN must remain low for at least 10
“clock cycle” after minimum VDD has been reached. For proper reset operation after the power-up
duration, RESET IN should be kept low a minimum of three clock periods. The CPU is held in the reset
condition as long as RESET IN is applied.
Reset Out: Reset Out indicates CPU is being reset. Can be used as a system reset. The signal is
synchronized to the processor clock and lasts an integral number of clock periods.
X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator. X, can
also be an external clock Input from a logic gate. The input frequency is divided by 2 to give the
processor’s internal operating frequency.
Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period.
Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM instruction
is executed.
Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction.
Power: +5V supply.
Ground: Reference.
PIN
NUMBER
11
9
8
7
6
I
RESET IN
36
I
RESET OUT
X1
X2
CLK
SID
SOD
VCC
GND
3
1
2
37
5
4
40
20
O
I
O
O
I
O
I
I
RESET IN
R1
VDD
C1
TYPICAL POWER-ON RESET RC VALUES (NOTE)
R1 = 75kΩ
C1 = 1µF
NOTE: Values may have to vary due to applied power supply ramp up time.
FIGURE 1. POWER-ON RESET CIRCUIT
4
HS-80C85RH
Waveforms
X
1
INPUT
CLK
OUTPUT
tXKR
tXKF
t1
t
r
t2
t
f
tCYC
FIGURE 2. CLOCK
T1
CLK
tLCK
A
8-15
ADDRESS
tAD
AD
0
-AD
7
tLL
ALE
tAL
RD/INTA
tAC
tLC
ADDRESS
tLA
tAFR
T2
T3
T1
tCA
tRAE
tRDH
DATA IN
tCL
tLDR
tRD
tCC
FIGURE 3. READ
T1
CLK
tLCK
A
8-15
ADDRESS
tLDW
AD
0
-AD
7
tLL
ALE
tAL
tLC
tAC
ADDRESS
tLA
T2
T3
T1
tCA
DATA OUT
tDW
tWDL
tCC
tWD
WR
tCL
FIGURE 4. WRITE
5
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