®
HI5800
Data Sheet
July 2000
File Number
2938.2
12-Bit, 3MSPS, Sampling A/D Converter
The HI5800 is a monolithic, 12-bit, sampling Analog-to-
Digital Converter fabricated in the HBC10 BiCMOS process.
It is a complete subsystem containing a sample and hold
amplifier, voltage reference, two-step subranging A/D, error
correction, control logic, and timing generator. The HI5800 is
designed for high speed applications where wide bandwidth,
accuracy and low distortion are essential.
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 3MSPS
• 12-Bit, No Missing Codes Over Temperature
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . 1.0 LSB
• Buffered Sample and Hold Amplifier
• Precision Voltage Reference
• Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . .
±2.5V
• 20MHz Input BW Allows Sampling Beyond Nyquist
• Zero Latency/No Pipeline Delay
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Applications
• High Speed Data Acquisition Systems
• Medical Imaging
Ordering Information
PART
NUMBER
HI5800BID
HI5800JCD
HI5800KCD
HI5800-EV
LINEARITY
±1
LSB
±2
LSB
±1
LSB
TEMP.
RANGE
(
o
C)
PACKAGE
PKG.
NO.
D40.6
D40.6
• Radar Signal Analysis
• Document and Film Scanners
• Vibration/Waveform Spectrum Analysis
• Digital Servo Control
-40 to 85 40 Ld SBDIP
0 to 70
25
40 Ld SBDIP
Evaluation Board
Pinout
HI5800
(SBDIP)
TOP VIEW
REF
IN
1
RO
ADJ
2
RG
ADJ
3
AV
CC
4
REF
OUT
5
V
IN
6
AGND 7
ADJ+ 8
ADJ- 9
AV
EE
10
AV
CC
11
AGND 12
AV
EE
13
A0 14
CS 15
OE 16
CONV 17
DV
EE
18
DGND 19
DV
CC
20
40 IRQ
39 OVF
38 AV
CC
37 D11 (MSB)
36 D10
35 D9
34 D8
33 DV
CC
32 DGND
31 AGND
30 AV
EE
29 D7
28 D6
27 D5
26 D4
25 D3
24 D2
23 D1
22 D0 (LSB)
21 AV
CC
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HI5800
Functional Block Diagram
D0 (LSB)
ERROR CORRECTION
OUTPUT LATCHES
REF
OUT
7-BIT
LATCH
REFERENCE
D1
D2
DIGITAL
OUTPUTS
D10
D11 (MSB)
OVF
ADJ+
ADJ-
7-BIT
DAC
CONTROL
LOGIC
AND
TIMING
IRQ
7-BIT
FLASH
CS
CONV
OE
AO
X32
REF
IN
7-BIT
LATCH
V
IN
S AND H
AV
CC
AV
EE
DV
CC
DV
EE
AGND
DGND
RG
ADJ
RO
ADJ
Typical Application Schematic
C23
C22
C1
+10µF
0.1µF
0.01µF
REF_IN (1)
REF_OUT (5)
AGND (7)
AGND (12)
AGND (31)
DGND (19)
DGND (32)
V
IN
V
IN
(6)
HI5800
(22) (LSB) D0
(23) D1
(24) D2
(25) D3
(26) D4
(27) D5
(28) D6
(29) D7
(34) D8
(35) D9
(36) D10
(40) IRQ
(39) OVF
CONV
OE
A0
CS
CONV (17)
OE (16)
A0 (14)
CS (15)
(18) DV
EE
(33) DV
CC
(20)
0.1µF
+
10µF
0.1µF
+
10µF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
IRQ
OVF
10µF, 0.1µF, AND 0.01µF CAPS ARE PLACED
AS CLOSE TO PART AS POSSIBLE
BNC
GND
(37) (MSB) D11
AV
CC
R9
10K
R10
10K
AV
EE
ADJ+ (8)
R11
10K
ADJ- (9)
RO_ADJ (2)
RG_ADJ (3)
(4) AV
CC
(11)
(21) AV
CC
(38)
(10) AV
EE
(13) (30)
+
0.1µF
10µF
0.1µF
10µF
+
4-2
HI5800
Absolute Maximum Ratings
Supply Voltages
AV
CC
or DV
CC
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
AV
EE
or DV
EE
to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±0.3V
Analog Input Pins
Reference Input REF
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . +2.75V
Signal Input V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . .
±(REF
IN
+0.2V)
RO
ADJ
, RG
ADJ
, ADJ+, ADJ- . . . . . . . . . . . . . . . . . . . . V
EE
to V
CC
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V
CC
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
40
15
Maximum Junction Temperature
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300
o
C
Operating Conditions
Temperature Range
HI5800JCD/KCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
HI5800BID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
CC
= +5V, DV
CC
= +5V, AV
EE
= -5V, DV
EE
= -5V; Internal Reference Used,
Unless Otherwise Specified
HI5800JCD
0
o
C TO 70
o
C
HI5800KCD, HI5800BID
0
o
C TO 70
o
C
-40
o
C TO 85
o
C
MAX
-
±2
±1
±15
-
±15
-
-
-
-
MIN
12
-
-
-
-
-
-
3.0
68
67
TYP
-
±0.5
±0.3
±2
±3
±2
±3
-
71
69
MAX
-
±1
±1
±15
±15
±15
±15
-
-
-
UNITS
Bits
LSB
LSB
LSB
LSB
LSB
LSB
MSPS
dB
dB
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
Offset Error, V
OS
(Adjustable to Zero)
Full Scale Error, FSE
(Adjustable to Zero)
TEST CONDITIONS
MIN
12
TYP
-
±0.7
±0.5
±2
-
±2
-
-
69
67
f
S
= 3MHz, f
IN
= 45Hz Ramp
f
S
= 3MHz, f
IN
= 45Hz Ramp
(Note 8)
(Note 8)
JCD, KCD
BID
JCD, KCD
BID
No Missing Codes
f
S
= 3MHz, f
IN
= 20kHz
f
S
= 3MHz, f
IN
= 1MHz
-
-
-
-
-
-
3.0
66
65
DYNAMIC CHARACTERISTICS
(Input Signal Level 0.5dB Below Full Scale)
Throughput Rate
Signal to Noise Ratio (SNR)
RMS Signal
-
= ------------------------------
RMS Noise
Signal to Noise Ratio (SINAD)
RMS Signal
-
= -------------------------------------------------------------
RMS Noise + Distortion
Total Harmonic Distortion, THD
Spurious Free Dynamic Range,
SFDR
Intermodulation Distortion, IMD
Differential Gain
Differential Phase
Aperture Delay, t
AD
f
S
= 3MHz, f
IN
= 20kHz
f
S
= 3MHz, f
IN
= 1MHz
f
S
= 3MHz, f
IN
= 20kHz
f
S
= 3MHz, f
IN
= 1MHz
f
S
= 3MHz, f
IN
= 20kHz
f
S
= 3MHz, f
IN
= 1MHz
f
S
= 3MHz, f
1
= 49kHz,
f
2
= 50kHz (Note 3)
f
S
= 1MHz
f
S
= 1MHz
(Note 3)
66
65
-
-
71
68
-
-
-
-
68
67
-74
-70
76
72
-74
0.9
0.05
12
-
-
-70
-68
-
-
-66
-
-
20
68
67
-
-
76
71
-
-
-
-
71
68
-85
-77
86
77
-79
0.9
0.05
12
-
-
-74
-70
-
-
-70
-
-
20
dB
dB
dBc
dBc
dBc
dBc
dBc
%
Degrees
ns
4-3
HI5800
Electrical Specifications
AV
CC
= +5V, DV
CC
= +5V, AV
EE
= -5V, DV
EE
= -5V; Internal Reference Used,
Unless Otherwise Specified
(Continued)
HI5800JCD
0
o
C TO 70
o
C
PARAMETER
Aperture Jitter, t
AJ
ANALOG INPUT
Input Voltage Range
Input Resistance
Input Capacitance
Input Current
Input Bandwidth
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage,
REF
OUT
(Loaded)
Reference Output Current
Reference Temperature
Coefficient
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
DIGITAL INPUTS
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic Current, I
IL
Digital Input Capacitance, C
IN
DIGITAL OUTPUTS
Output Logic High Voltage, V
OH
Output Logic Low Voltage, V
OL
Output Logic High Current, I
OH
Output Logic Low Current, I
OL
Output Three-State Leakage
Current, I
OZ
Digital Output Capacitance, C
OUT
TIMING CHARACTERISTICS
Minimum CONV Pulse, t
1
CS to CONV Setup Time, t
2
CONV to CS Setup Time, t
3
Minimum OE Pulse, t
4
CS to OE Setup Time, t
5
OE to CS Setup Time, t
6
IRQ Delay from Start Convert, t
7
IRQ Pulse Width, t
8
Minimum Cycle Time for
Conversion, t
9
IRQ to Data Valid Delay, t
10
Minimum A0 Pulse, t
11
(Note 3)
(Notes 3, 5)
(Notes 3, 4)
(Note 3)
(Note 3)
(Notes 3, 5)
(Note 3)
(Note 3)
(Note 3)
JCD, KCD
BID
10
10
0
15
0
0
10
190
-
-
-5
10
-
-
-
-
-
-
20
200
-
325
0
-
-
-
-
-
-
-
25
230
-
333
+5
-
10
10
0
15
0
0
10
190
180
-
-5
10
-
-
-
-
-
-
20
200
195
325
0
-
-
-
-
-
-
-
25
230
230
333
+5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
OUT
= 0V, 5V
I
OUT
= -160µA
I
OUT
= 3.2mA
2.4
-
-0.160
3.2
-
-
4.3
0.22
-6
6
±±1
10
-
0.4
-
-
±10
-
2.4
-
-0.160
3.2
-
-
4.3
0.22
-6
6
±1
10
-
0.4
-
-
±10
-
V
V
mA
mA
µA
pF
V
IN
= 0V, 5V
V
IN
= 0V
(Note 6)
2.0
-
-
-
-
-
±±1
5
-
0.8
±10
-
2.0
-
-
-
-
-
±1
5
-
0.8
±10
-
V
V
µA
pF
-
-
2.5
200
2.6
-
-
-
2.5
200
2.6
-
V
Ω
(Note 5)
2.450
2
-
2.500
-
20
2.550
-
-
2.470
2
-
2.500
-
13
2.530
-
-
V
mA
ppm /
o
C
-
1
-
-
-
±2.5
3
5
±1
20
±2.7
-
-
±10
-
-
1
-
-
-
±2.5
3
5
±1
20
±2.7
-
-
±10
-
V
MΩ
pF
µA
MHz
TEST CONDITIONS
(Note 3)
MIN
-
TYP
10
MAX
20
MIN
-
HI5800KCD, HI5800BID
0
o
C TO 70
o
C
-40
o
C TO 85
o
C
TYP
10
MAX
20
UNITS
ps
4-4
HI5800
Electrical Specifications
AV
CC
= +5V, DV
CC
= +5V, AV
EE
= -5V, DV
EE
= -5V; Internal Reference Used,
Unless Otherwise Specified
(Continued)
HI5800JCD
0
o
C TO 70
o
C
PARAMETER
Data Access from OE Low, t
12
LSB, Nibble Delay from A0 High, t
13
MSB Delay from A0 Low, t
14
CS to Float Delay, t
15
Minimum CS Pulse, t
16
CS to Data Valid Delay, t
17
Output Fall 2 Time, t
f
Output Rise Time, t
r
IV
CC
IV
EE
IDV
CC
IDV
EE
Power Dissipation
PSRR
NOTES:
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Parameter guaranteed by design or characterization and not production tested.
4. Recommended pulse width for CONV is 60ns.
5. Recommended minimum pulse width is 25ns.
7. The A0 pin V
IH
at -40
o
C may exceed 2.0V by up to 0.4V at initial power up.
8. Excludes error due to internal reference temperature drift.
6. This is the additional current available from the REF
OUT
pin with the REF
OUT
pin driving the REF
IN
pin.
V
CC
, V
EE
±5%
TEST CONDITIONS
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Notes 3, 5)
(Note 3)
(Note 3)
(Note 3)
MIN
10
-
-
10
15
10
-
-
-
-
-
-
-
-
TYP
18
10
14
18
-
18
5
5
170
150
24
2
1.7
0.01
MAX
25
20
20
25
-
25
20
20
220
190
40
5
2.2
-
MIN
10
-
-
10
15
10
-
-
-
-
-
-
-
-
HI5800KCD, HI5800BID
0
o
C TO 70
o
C
-40
o
C TO 85
o
C
TYP
18
10
14
18
-
18
5
5
170
150
24
2
1.7
±0.01
MAX
25
20
20
25
-
25
20
20
220
190
40
5
2.2
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
mA
mA
mA
mA
W
% /%
POWER SUPPLY CHARACTERISTICS
Timing Diagrams
CONV
t
1
CS
t
16
t
7
IRQ
ACQUIRE N
N CONVERSION
t
8
DATA VALID
N - 1 DATA
N DATA
AO
OE
t
15
D0 - D11, OVF
t
12
N DATA
t
17
FIGURE 1. SINGLE SHOT TIMING
4-5
NXP MCU
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