®
HI-5701
Data Sheet
September 9, 2005
FN2937.10
6-Bit, 30MSPS, Flash A/D Converter
The HI-5701 is a monolithic, 6-bit, CMOS flash Analog-to-
Digital Converter. It is designed for high speed applications
where wide bandwidth and low power consumption are
essential. Its 30MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5701 delivers
±0.7
LSB
differential nonlinearity while consuming only 250mW (Typ)
at 30MSPS. Microprocessor compatible data output latches
are provided which present valid data to the output bus 1.5
clock cycles after the convert command is received. An
overflow bit is provided to allow the series connection of two
converters to achieve 7-bit resolution.
Features
• 30MSPS with No Missing Codes
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . . 20MHz
• No Missing Codes Over Temperature
• Sample and Hold Not Required
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V
• Power Dissipation (Max). . . . . . . . . . . . . . . . . . . . .300mW
• CMOS/TTL Compatible
• Overflow Bit
Applications
Ordering Information
PART NUMBER
HI9P5701K-5
TEMP.
RANGE (
o
C)
0 to 70
PACKAGE
18 Ld SOIC
PKG.
DWG. #
M18.3
• Video Digitizing
• Radar Systems
• Communication Systems
• High Speed Data Acquisition Systems
Pinout
HI-5701
(SOIC)
TOP VIEW
D5 (MSB)
OVF
V
SS
NC
CE2
CE1
CLK
PHASE
V
REF
+
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
D4
D3
1
/ R
2
D2
D1
D0 (LSB)
V
DD
V
IN
V
REF
-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or
1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-5701
Functional Block Diagram
φ1
φ2
φ1
φ1
φ2
V
IN
R/2
V
REF
+
COMP 64
R
D
Q
CL
D5 (MSB)
D
Q
CL
OVERFLOW
(OVF)
R
COMP 63
R
1
/ R
2
D
Q
CL
D4
R
COMP 32
R
COMPARATOR
LATCHES
AND
63 TO 6
ENCODER
LOGIC
D
Q
CL
D3
D
Q
CL
D2
R
COMP 2
D
Q
CL
D1
V
REF
-
R/2
COMP 1
D
Q
CL
D0 (LSB)
CE1
CE2
CLOCK
φ2
(SAMPLE)
φ1
(AUTO BALANCE)
V
DD
V
SS
PHASE
2
HI-5701
Absolute Maximum Ratings
Supply Voltage, V
DD
to V
SS
. . . . . . . . . . . (V
SS
-
0.5) < V
DD
< +7V
Analog and Reference Input Pins (V
SS
-
0.5) < V
INA
< (V
DD
+0.5V)
Digital I/O Pins . . . . . . . . . . . . . . . .(V
SS
-
0.5) < V
I/O
< (V
DD
+0.5V)
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
Operating Conditions
Temperature Range
HI9P5701-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Power Dissipation at 70
o
C (Note 2) . . . . . . . . . . .635mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
Electrical Specifications
V
DD
= +5.0V; V
REF
+ = +4.0V; V
REF-
= V
SS
= GND; f
S
= Specified Clock Frequency at 50% Duty Cycle;
C
L
= 30pF; Unless Otherwise Specified
25
o
C
0
o
C TO 70
o
C
MAX
MIN
MAX
UNITS
(NOTE 3)
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
(Best Fit Line)
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
Offset Error, V
OS
(Adjustable to Zero)
Full Scale Error, FSE
(Adjustable to Zero)
DYNAMIC CHARACTERISTICS
Maximum Conversion Rate
Minimum Conversion Rate
Full Power Input Bandwidth
Signal to Noise Ratio, SNR
RMS Signal
= --------------------------------
-
RMS Noise
Signal to Noise Ratio, SINAD
RMS Signal
= -------------------------------------------------------------
-
RMS Noise + Distortion
Total Harmonic Distortion
TEST CONDITIONS
MIN
TYP
6
f
S
= 20MHz
f
S
= 30MHz
f
S
= 20MHz
f
S
= 30MHz
f
S
= 20MHz (Note 3)
f
S
= 30MHz
f
S
= 20MHz (Note 3)
f
S
= 30MHz
-
-
-
-
-
-
-
-
-
±0.5
±1.5
±0.3
±0.7
±0.5
±0.5
±0.25
±0.25
-
±1.25
-
±0.6
-
±2.0
-
±2.0
-
6
-
-
-
-
-
-
-
-
-
±2.0
-
±0.75
Bits
LSB
LSB
LSB
LSB
±2.5
-
±2.5
-
LSB
LSB
LSB
LSB
No Missing Codes
No Missing Codes (Note 3)
f
S
= 30MHz
f
S
= 1MHz, f
IN
= 100kHz
f
S
= 30MHz, f
IN
= 4MHz
30
-
-
-
-
40
-
20
36
31
-
0.125
-
-
-
30
-
-
-
-
-
0.125
-
-
-
MSPS
MSPS
MHz
dB
dB
f
S
= 1MHz, f
IN
= 100kHz
f
S
= 30MHz, f
IN
= 4MHz
f
S
= 1MHz, f
IN
= 100kHz
f
S
= 30MHz, f
IN
= 4MHz
-
-
35
30
-
-
-
-
-
-
dB
dB
-
-
-
-
-
44
-
38
2
2
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
%
Degree
Differential Gain
Differential Phase
ANALOG INPUTS
Analog Input Resistance, R
IN
Analog Input Capacitance, C
IN
f
S
= 14.32MHz, f
IN
= 3.58MHz
f
S
= 14.32MHz, f
IN
= 3.58MHz
V
IN
= 4V
V
IN
= 0V
-
-
30
20
-
-
-
-
-
-
MΩ
pF
3
HI-5701
Electrical Specifications
V
DD
= +5.0V; V
REF
+ = +4.0V; V
REF-
= V
SS
= GND; f
S
= Specified Clock Frequency at 50% Duty Cycle;
C
L
= 30pF; Unless Otherwise Specified
(Continued)
(NOTE 3)
25
o
C
PARAMETER
Analog Input Bias Current, IB
REFERENCE INPUTS
Total Reference Resistance, R
L
Reference Resistance Tempco, T
C
DIGITAL INPUTS
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic High Current, I
IH
Input Logic Low Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS
Output Logic Sink Current, I
OL
Output Logic Source Current, I
OH
Output Leakage, I
OFF
Output Capacitance, C
OUT
TIMING CHARACTERISTICS
Aperture Delay, t
AP
Aperture Jitter, t
AJ
Data Output Enable Time, t
EN
Data Output Disable Time, t
DIS
Data Output Delay, t
OD
Data Output Hold, t
H
POWER SUPPLY REJECTION
Offset Error PSRR,
∆V
OS
Gain Error PSRR,
∆FSE
POWER SUPPLY CURRENT
Supply Current, I
DD
NOTE:
3. Parameter guaranteed by design or characterization and not production tested.
f
S
= 20MHz
-
50
60
-
75
mA
V
DD
= 5V
±10%
V
DD
= 5V
±10%
-
-
±0.1
±0.1
±1.0
±1.0
-
-
±1.5
±1.5
LSB
LSB
(Note 3)
(Note 3)
(Note 3)
(Note 3)
-
-
-
-
-
5
6
30
12
11
14
10
-
-
20
20
20
-
-
-
-
-
-
5
-
-
20
20
20
-
ns
ps
ns
ns
ns
ns
V
O
= 0.4V
V
O
= 4.5V
CE2 = 0V
CE2 = 0V
3.2
-3.2
-
-
-
-
-
5.0
-
-
±1.0
-
3.2
-
-
±1.0
-
mA
mA
µA
pF
V
IN
= 5V
V
IN
= 0V
2.0
-
-
-
-
-
-
-
-
7
-
0.8
1.0
1.0
-
2.0
-
-
-
-
-
0.8
1.0
1.0
-
V
V
µA
µA
pF
250
-
370
+0.266
-
-
235
-
-
-
Ω
Ω/
o
C
TEST CONDITIONS
V
IN
= 0V, 4V
MIN
-
TYP
0.01
MAX
±1.0
0
o
C TO 70
o
C
MIN
-
MAX
±1.0
UNITS
µA
-
3.2
-
-
4
HI-5701
Timing Waveforms
COMPARATOR DATA
IS LATCHED
CLOCK
INPUT
PHASE - HIGH
ENCODED DATA IS
LATCHED INTO THE
OUTPUT REGISTERS
φ
2
φ
1
φ
2
φ
1
φ
2
φ
1
φ
2
φ
1
φ
2
CLOCK
INPUT
PHASE - LOW
SAMPLE
N-2
AUTO
BALANCE
t
AB
SAMPLE
N-1
t
S
AUTO
BALANCE
SAMPLE
N
AUTO
BALANCE
SAMPLE
N+1
AUTO
BALANCE
SAMPLE
N+2
ANALOG
INPUT
t
AP
t
AJ
t
H
t
OD
DATA
OUTPUT
DATA N - 4
DATA N - 3
DATA N - 2
DATA N - 1
DATA N
FIGURE 1. INPUT-TO-OUTPUT TIMING
CE1
CE2
t
DIS
t
EN
t
DIS
t
EN
D0
-
D5
DATA
HIGH
IMPEDANCE
DATA
HIGH
IMPEDANCE
DATA
OVF
DATA
HIGH
IMPEDANCE
DATA
FIGURE 2. OUTPUT ENABLE TIMING
5
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