CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Unless Otherwise Specified, Typical parameters at 25
o
C, Min-Max parameters are over operating
temperature range. V
DD
= 5V.
SYMBOL
MIN
TYP
MAX
UNITS
PARAMETER
STATIC SPECIFICATIONS
Quiescent Device Current
Operating Device Current
OUT1, OUT2 Low (Sink) Current
(V
OL
= 0.4V)
All Other Outputs Low (Sink) Current
(V
OL
= 0.8V)
All Outputs High (Source) Current
(V
OH
= 4V)
Input Low Current
Input High Current
Input Low Voltage
Input High Voltage
Input Capacitance
l
DD
-
-
-
10
-
-
-
-
-
-
-
-
100
-
-
-
-
10
10
0.8
-
8
µA
mA
mA
mA
mA
µA
µA
V
V
pF
I
OL1
I
OL2
I
OH
I
IL
I
IH
V
lL
V
lH
C
lN
3.2
2
2
-
-
-
2.4
-
Electrical Specifications
Unless Otherwise Specified, Typical parameters at 25
o
C, Min-Max parameters are over operating
temperature range. V
DD
= 5V.
SYMBOL
FIGURE
MIN
TYP
MAX
UNITS
PARAMETER
DYNAMIC SPECIFICATIONS
CLK ENC, CLK DEC Input Frequency
CLK ENC, CLK DEC Rise Time (1.544MHz)
Fall Time
Rise Time (2.048MHz)
Fall Time
Rise Time (6.3212MHz)
Fall Time
Rise Time (8.448MHz)
Fall Time
f
CL
t
RCL
t
FCL
t
RCL
t
FCL
t
RCL
t
FCL
t
RCL
t
FCL
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
-
-
-
-
-
-
-
-
-
-
10
10
10
10
10
10
5
5
8.5
60
60
40
40
30
30
10
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
2
HC-5560
Electrical Specifications
Unless Otherwise Specified, Typical parameters at 25
o
C, Min-Max parameters are over operating
temperature range. V
DD
= 5V.
(Continued)
SYMBOL
t
S
t
H
t
S
t
H
t
DD
t
W
t
W
t
W
t
W
t
DD
t
S2
t
H2
t
S2
t
PD5
t
PD4
FIGURE
1
1
2
2
1
MIN
20
20
15
5
-
TYP
-
-
-
-
23
MAX
-
-
-
-
80
UNITS
ns
ns
ns
ns
ns
PARAMETER
NRZ-Data In to CLK ENC Data Setup Time
Data Hold Time
A
IN
, B
IN
to CLK DEC Data Setup Time
Data Hold Time
CLK ENC to OUT1, OUT2
OUT1, OUT2 Pulse Width (CLK ENC Duty Cycle = 50%)
f
CL
= 1.544MHz
f
CL
= 2.048MHz
f
CL
= 6.3212MHz
f
CL
=
8.448MHz
CLK DEC to NRZ-Data Out
Setup Time CLK DEC to Reset AlS
Hold Time of Reset AlS = ‘0’
Setup Time Reset AlS = ‘1’ to CLK DEC
Reset AlS to AIS Output
CLK DEC to Error Output
1
1
1
1
2
3
3
3
3
3
-
-
-
-
-
35
20
0
-
-
324
224
79
58
25
-
-
-
-
-
-
-
-
-
54
-
-
-
42
62
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pin Descriptions
PIN NUMBER
1
2, 5
FUNCTION
Force AIS
Mode Select 1,
Mode Select 2
DESCRIPTION
Pin 19 must be at logic ‘0’ to enable this pin. A logic ‘1’ on this pin forces OUT1 and OUT2 to all ‘1’s. A logic
‘0’ on this pin allows normal operation.
MS1
0
0
1
1
MS2
0
1
0
1
Functions As
AMI
B8ZS
B6ZS
HDB3
3
4
6
7
8, 9
NRZ Data In
CLK ENC
NRZ Data Out
CLK DEC
Reset AIS, AlS
Input data to be encoded into ternary form. The data is clocked by the negative going edge of CLK ENC.
Clock encoder, clock for encoding data at NRZ Data In.
Decoded data from ternary inputs A
IN
and B
IN
.
Clock decoder, clock for decoding ternary data on inputs A
IN
and B
IN
.
Logic ‘0’ on Reset AIS resets a decoded zero counter and either resets AIS output to zero provided 3 or more
zeros have been decoded in the preceding Reset AIS period or sets AlS to ‘1’ if less than 3 zeros have been
decoded in the preceding two Reset AlS periods. A period of Reset AlS is defined from the bit following the
bit during which Reset AlS makes a high to low transition to the bit during which Reset AIS makes the next
high to low transition.
Ground reference.
A logic ‘1’ indicates that a violation of the line coding scheme has been decoded.
“OR” function of A
IN
and B
IN
for clock regeneration when pin 14 is at logic ‘0’, “OR” function of OUT1 and
OUT2 when pin 14 is at logic ‘1’.
Inputs representing the received PCM signal. A
IN
= ‘1’ represents a positive going ‘1’ and B
IN
= ‘1’ represents
a negative going ‘1’. A
IN
and B
IN
are sampled by the positive going edge of CLK DEC. A
IN
and B
IN
may be
interchanged.
10
11
12
13, 15
V
SS
Error
Clock
A
IN
, B
IN
3
HC-5560
Pin Descriptions
PIN NUMBER
14
(Continued)
DESCRIPTION
Loop Test Enable, this pin selects between normal and loop back operation. A logic ‘0’ selects normal
operation where encode and decode are independent and asynchronous. A logic ‘1’ selects a loop back
condition where OUT1 is internally connected to A
IN
and OUT2 is internally connected to B
IN
. A decode clock
must be supplied.
Outputs representing the ternary encoded NRZ Data In signal for line transmission. OUT1 and OUT2 are in
return to zero form and are clocked out on the positive going edge of CLK ENC. The length of OUT1 and
OUT2 is set by the length of the positive clock pulse.
A logic ‘0’ on this pin resets all internal registers to zero. A logic ‘1’ allows normal operation of all internal
registers.
A logic ‘1’ on this pin forces outputs OUT1 and OUT2 to zero. A logic ‘0’ allows normal operation.
Power to chip.
FUNCTION
LTE
16, 17
OUT1, OUT2
18
19
20
Reset
Output Enable
V
DD
Functional Description
The HC-5560 TRANSCODER can be divided into six sections:
transmission (coding), reception (decoding), error detection, all
ones detection, testing functions, and output controls.
The transmitter codes a non-return to zero (NRZ) binary
unipolar input signal (NRZ Data In) into two binary unipolar
return to zero (RZ) output signals (OUT1, OUT2). These
output signals represent the NRZ data stream modified
according to the selected encoding scheme (i.e., AMl, B8ZS,
B6ZS, HDB3) and are externally mixed together (usually via
a transistor or transformer network) to create a ternary
bipolar signal for driving transmission lines.
The receiver accepts as its input the ternary data from the
transmission line that has been externally split into two binary
unipolar return to zero signals (A
IN
and B
IN
). These signals are
decoded, according to the rules of the selected line code into
one binary unipolar NRZ output signal (NRz Data Out).
The encoder and decoder sections of the chip perform
independently (excluding loopback condition) and may
operate simultaneously.
The Error output signal is active high for one cycle of CLK
DEC upon the detection of any bipolar violation in the
received A
IN
and B
IN
signals that is not part of the selected
line coding scheme. The bipolar violation is not removed,
however, and shows up as a pulse in the NRZ Data Out
signal. In addition, the Error output signal monitors the
received A
IN
and B
IN
signals for a string of zeros that
violates the maximum consecutive zeros allowed for the
selected line coding scheme (i.e., 15 for AMI, 8 for B8ZS, 6
for B6ZS, and 4 for HDB3). ln the event that an excessive
amount of zeros is detected, the Error output signal will be
active high for one cycle of CLK DEC during the zero that
exceeds the maximum number. In the case that a high level
should simultaneously appear on both received input signals
A
IN
and B
IN
a logical one is assumed and appears on the
NRZ Data Out stream with the Error output active.
An input signal received at inputs A
IN
and B
IN
that consists
of all ones (or marks) is detected and signaled by a high
level at the Alarm Indication Signal (AlS) output. This is also
known as Blue Code. The AlS output is set to a high level
when less than three zeros are received during one period of
Reset AIS immediately followed by another period of Reset
AlS containing less than three zeros. The AIS output is reset
to a low level upon the first period of Reset AlS containing 3
or more zeros.
A logic high level on LTE enables a loopback condition
where OUT1 is internally connected to A
IN
and OUT2 is
internally connected to B
IN
(this disables inputs A
IN
and B
IN
to external signals). In this condition, NRZ Data In appears
at NRZ Data Out (delayed by the amount of clock cycles it
takes to encode and decode the selected line code). A
decode clock must be supplied for this operation.
The output controls are Output Enable and Force AlS. These
pins allow normal operation, force OUT1 and OUT2 to zero,
or force OUT1 and OUT2 to output all ones (AIS condition).
Line Code Descriptions
AMl, Alternate Mark Inversion, is used primarily in North
American T1 (1.544MHz) and T1C (3.152MHz) carriers.
Zeros are coded as the absence of a pulse and ones are
coded alternately as positive or negative pulses. This type of
coding reduces the average voltage level to zero to eliminate
DC spectral components, thereby eliminating DC wander. To
simplify timing recovery, logic 1’s are encoded with 50% duty
cycle pulses.
e.g.,
PCM CODE
AMI CODE
0
0
0
1
0 1
1
1
0 1
0
0
0 0
0 1
To facilitate timing maintenance at regenerative repeaters
along a transmission path, a minimum pulse density of logic
1’s is required. Using AMl, there is a possibility of long
strings of zeros and the required density may not always
exist, leading to timing jitter and therefore higher error rates.
4
HC-5560
A method for insuring minimum logic 1 density by substituting
bipolar code in place of strings of 0’s is called BNZS or Bipolar
with N Zero Substitution. B6ZS is used commonly in North
American T2 (6.3212MHz) carriers. For every string of 6
zeros, bipolar code is substituted according to the following
rule:
• If the immediate preceding pulse is of (-) polarity, then
code each group of 6 zeros as 0+- 0+-, and if the
immediate preceding pulse is of (+) polarity, code each
group of 6 zeros as 0+- 0-+.
One can see the consecutive logic 1 pulses of the same
polarity violate the AMI coding scheme.
e.g.,
6
PCM CODE
0
0
0
1
0
1 1 1 0 0
0
B6ZS (
-
)
V
V
0
B6ZS (+)
V
V
V = VIOLATION
+
0
0
0
+
0
0
0
+
0
1
HDB3 (-)
PCM CODE
Another coding scheme is HDB3, high density bipolar 3, used
primarily in Europe for 2.048MHz and 8.448MHz carriers. This
code is similar to BNZS in that it substitutes bipolar code for 4
consecutive zeros according to the following rule:
1. If the polarity of the immediate preceding pulse is (-) and
there have been an odd (even) number of logic 1 pulses
since the last substitution, each group of 4 consecutive
zeros is coded as 000-(+00+).
2. If the polarity of the immediate preceding pulse is (+) then
the substitution is 000+(-00-) for odd (even) number of
logic 1 pulses since the last substitution.
e.g.,
4
0 0 0 0 1 0 1
0 0
0
1 1
0 0
+
4
0 0
0
0 1
-
V
0 0 +
-
+ 0
-
V
-
0
0
-
V
-
0
-
+
HDB3 (+)
V
V = VIOLATION
B8ZS is used commonly in North American T1 (1.544MHz)
and T1C (3.152MHz) carriers. For every string of 8 zeros,
bipolar code is substituted according to the following rules:
1. If the immediate preceding pulse is of (-) polarity, then
code each group of 8 zeros as 000-+ 0+-.
2. If the immediate preceding pulse is of (+) polarity then
code each group of 8 zeros as 000+-0-+.
e.g.,
8
The 3 in HDB3 refers to the coding format that precludes
strings of zeros greater than 3. Note that violations are
produced only in the fourth bit location of the substitution
code and that successive substitutions produce alternate
polarity violations.
PCM CODE
1 0 1 0
0
0
0
0
0
0
0
0
0
+
0
1
1
0
-
V
+ 0
-
B8ZS (
-
)
V
0
B8ZS (+)
0
0
+
-
0
-
+
V
V = VIOLATION
The BNZS coding schemes, in addition to eliminating DC
wander, minimize timing jitter and allow a line error
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