®
80C88
CMOS 8/16-Bit Microprocessor
Description
The Intersil 80C88 high performance 8/16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, MINimum
for small systems and MAXimum for larger applications such
as multiprocessing, allow user configuration to achieve the
highest performance level.
Full TTL compatibility (with the exception of CLOCK) and
industry-standard operation allow use of existing NMOS
8088 hardware and Intersil CMOS peripherals.
Complete software compatibility with the 80C86, 8086, and
8088 microprocessors allows use of existing software in new
designs.
November 2004
Features
• Compatible with NMOS 8088
• Direct Software Compatibility with 80C86, 8086, 8088
• 8-Bit Data Bus Interface; 16-Bit Internal Architecture
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8MHz (80C88-2)
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . 10mA/MHz Maximum
• 1 Megabyte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word, and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
• Bus-Hold Circuitry Eliminates Pull-up Resistors
• Wide Operating Temperature Ranges
- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to + 70
o
C
- I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M80C88 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Ordering Information
PACKAGE
PDIP
TEMPERATURE RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
CERDIP
-55
o
C to +125
o
C
CP80C88
IP80C88
MD80C88/B
5MHz
8MHz
CP80C88-2
IP80C88-2
PKG. DWG. #
E40.6
E40.6
F40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Harris Corporation 1997, Copyright Intersil Americas Inc. 2004. All Rights Reserved
1
FN2949.3
80C88
Pinout
80C88 (PDIP, CERIDP)
TOP VIEW
GND
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MIN
MODE
40 V
CC
39 A15
38 A16/S3
37 A17/S4
36 A18/S5
35 A19/S6
34 SS0
33 MN/MX
32 RD
31 HOLD
30 HLDA
29 WR
28 IO/M
27 DT/R
26 DEN
25 ALE
24 INTA
23 TEST
22 READY
21 RESET
(RQ/GT0)
(RQ/GT1)
(LOCK)
(S2)
(S1)
(S0)
(QS0)
(QS1)
(HIGH)
MAX
MODE
2
80C88
Functional Diagram
EXECUTION UNIT
REGISTER FILE
DATA POINTER
AND
INDEX REGS
(8 WORDS)
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
SSO/HIGH
16-BIT ALU
FLAGS
BUS
INTERFACE
UNIT
8
8
3
4
4
A19/S6. . . A16/S3
AD7-AD0
A8-A15
INTA, RD, WR
DT/R, DEN, ALE, IO/M
4-BYTE
INSTRUCTION
QUEUE
TEST
INTR
NMI
RQ/GT0, 1
HOLD
HLDA
3
RESET READY MN/MX GND
V
CC
2
CONTROL AND TIMING
LOCK
2
3
QS0, QS1
S2, S1, S0
CLK
MEMORY INTERFACE
C-BUS
B-BUS
ES
BUS
INTERFACE
UNIT
CS
SS
DS
IP
INSTRUCTION
STREAM BYTE
QUEUE
EXECUTION UNIT
CONTROL SYSTEM
A-BUS
AH
BH
CH
EXECUTION
UNIT
DH
SP
BP
SI
DI
AL
BL
CL
DL
ARITHMETIC/
LOGIC UNIT
FLAGS
3
80C88
Pin Description
The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “local bus” in these
descriptions is the direct multiplexed bus interface connection to the 80C88 (without regard to additional bus buffers).
SYMBOL
AD7-AD0
PIN
NUMBER
9-16
TYPE
I/O
DESCRIPTION
ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and
data (T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last
valid level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”
ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4).
These lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held
at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold
acknowledge” or “grant sequence”.
ADDRESS/STATUS: During T1, these are the four most
significant address lines for memory operations. During I/O
operations, these lines are LOW. During memory and I/O
operations, status information is available on these lines
during T2, T3, TW and T4. S6 is always LOW. The status
of the interrupt enable flag bit (S5) is updated at the begin-
ning of each clock cycle. S4 and S3 are encoded as
shown.
This information indicates which segment register is
presently being used for data accessing.
These lines are held at high impedance to the last valid
logic level during local bus “hold acknowledge” or “grant
Sequence”.
S4
0
0
1
1
S3
0
1
0
1
CHARACTERISTICS
Alternate Data
Stack
Code or None
Data
A15-A8
2-8, 39
O
A19/S6,
A18/S5,
A17/S4,
A16/S3
35
36
37
38
O
O
O
O
RD
32
O
READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depend-
ing on the state of the IO/M pin or S2. This signal is used to read devices which reside on the 80C88
local bus. RD is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH
in T2 until the 80C88 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.
READY: is the acknowledgment from the address memory or I/O device that it will complete the data
transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from
READY. This signal is active HIGH. The 80C88 READY input is not synchronized. Correct operation
is not guaranteed if the set up and hold times are not met.
INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of
each instruction to determine if the processor should enter into an interrupt acknowledge operation.
A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be
internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This
signal is active HIGH.
TEST: input is examined by the “wait for test” instruction. If the TEST input is LOW, execution con-
tinues, otherwise the processor waits in an “idle” state. This input is synchronized internally during
each clock cycle on the leading edge of CLK.
NONMASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A sub-
routine is vectored to via an interrupt vector lookup table located in system memory. NMI is not
maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end
of the current instruction. This input is internally synchronized.
RESET: cases the processor to immediately terminate its present activity. The signal must transition
LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as de-
scribed in the instruction set description, when RESET returns LOW. RESET is internally synchro-
nized.
CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33%
duty cycle to provide optimized internal timing.
V
CC
: is the +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 recommended for de-
coupling.
GND: are the ground pins (both pins must be connected to system ground). A 0.1µF capacitor be-
tween pins 1 and 20 is recommended for decoupling.
READY
22
I
INTR
18
I
TEST
23
I
NMI
17
I
RESET
21
I
CLK
V
CC
GND
MN/MX
19
40
1, 20
33‘
I
I
MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are
discussed in the following sections.
4
80C88
Pin Description
(Continued)
The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/MX = V
CC
). Only the pin functions
which are unique to the minimum mode are described; all other pin functions are as described above.
MINIMUM MODE SYSTEM
PIN
NUMBER
28
SYMBOL
IO/M
TYPE
O
DESCRIPTION
STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from
an I/O access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final
T4 of the cycle (I/O = HIGH, M = LOW). IO/M is held to a high impedance logic one during local bus
“hold acknowledge”.
Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depend-
ing on the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active
LOW, and is held to high impedance logic one during local bus “hold acknowledge”.
INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and
Tw of each interrupt acknowledge cycle. Note that INTA is never floated.
ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the
82C82/82C83 address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note
that ALE is never floated.
DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87
data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T = HIGH, R
= LOW). This signal is held to a high impedance logic one during local bus “hold acknowledge”.
DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which
uses the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles.
For a read or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write
cycle, it is active from the beginning of T2 until the middle of T4. DEN is held to high impedance logic
one during local bus “hold acknowledge”.
HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD
must be active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an
acknowledgment, in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA
the processor will float the local bus and control lines. After HOLD is detected as being LOW, the
processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the
local bus and control lines.
Hold is not an asynchronous input. External synchronization should be provided if the system cannot
otherwise guarantee the set up time.
STATUS LINE: is logically equivalent to S0
in the maximum mode. The combination of
SS0, IO/M and DT/R allows the system to
completely decode the current bus cycle
status. SS0 is held to high impedance logic
one during local bus “hold acknowledge”.
IO/M
1
1
1
1
0
0
0
0
DT/R
0
0
1
1
0
0
1
1
SS0
0
1
0
1
0
1
0
1
CHARACTERISTICS
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
WR
29
O
INTA
24
O
ALE
25
O
DT/R
27
O
DEN
26
O
HOLD,
HLDA
31
30
I
O
SS0
34
O
5
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