Total-AceXtreme
®
Ultra-Small, Ultra-Low Power
MIL-STD-1553 Single Package Solution
Model: BU-67301B
Data Sheet
World's smallest, ultra low power, fully integrated MIL-STD-1553 BGA package,
complete with 1553 protocol,
2 Mb (64K x 36) RAM, transceivers, and isolation transformers inside a single package — saves board space and
simplifies 1553 design and layout. Available with development kit to ease integration.
Features
•
Small, Fully Integrated 1553 Terminal with
Transformers Inside:
- 16 x 16 x 4.7 mm (0.63 x 0.63 x 0.185 in.)
- Protocol, RAM, Transceivers and Transformers in a
Single Package
- 324 Ball JEDEC Design Guide 4.5 Standard Size
Fine Pitch Ball Grid Array with 0.8 mm Ball Pitch
•
Ultra Low Transceiver Power
•
Comprehensive Built-in Self Test
•
Versatile User Selectable High-Speed Backend for
PCI or CPU Interface
- Access Time as low as 12.5ns
- DMA Engine with 264MB/sec Burst Transfer Rate
•
1
-
-
-
-
-
-
-
Dual Redundant MIL-STD-1553 Channel
BC or Multi-RT with Concurrent Bus Monitor
Supports MIL-STD-1553 A/B and MIL-STD-1760
2 Mb (64K x 36) RAM
Tx Inhibit Ball for MT Only Applications
BC Disable Ball for RT Only Applications
48-bit/100ns Time Stamp
IRIG-106 Chapter 10 MT Support
•
Supports JTAG Boundary Scan
•
IRIG-B Input
•
8 Digital Discrete I/O
•
Hardware/Software Development Kit with PCI
Evaluation Board and Reference Design Artifacts
For more information:
www.ddc-web.com/BU-67301B
© 2011 Data Device Corporation. All trademarks are the property of their respective owners.
DDC's Data Networking Solutions
MIL-STD-1553 | ARINC 429 | Fibre Channel
As the leading global supplier of data bus components, cards, and software solutions for the military, commercial,
and aerospace markets, DDC’s data bus networking solutions encompass the full range of data interface
protocols from MIL-STD-1553 and ARINC 429 to USB, and Fibre Channel, for applications utilizing a spectrum of
form-factors including PMC, PCI, Compact PCI, PC/104, ISA, and VME/VXI.
DDC has developed its line of high-speed Fibre Channel and Extended 1553 products to support the real-time
processing of field-critical data networking netween sensors, compute notes, data storage displays, and weapons
for air, sea, and ground military vehicles.
Whether employed in increased bandwidth, high-speed serial communications, or traditional avionics and ground
support applications, DDC's data solutions fufill the expanse of military requirements including reliability,
determinism, low CPU utilization, real-time performance, and ruggedness within harsh environments. Out use of
in-house intellectual property ensures superior mutli-generational support, independent of the life cycles of
commercial devices. Moreover, we maintain software compatibility between product generations to protect our
customers' investments in software development, system testing, and end-product qualification.
MIL-STD-1553
DDC provides an assortment of quality MIL-STD-1553 commercial, military, and COTS grade cards and
components to meet your data conversion and data interface needs. DDC supplies MIL-STD-1553 board level
products in a variety of form factors including AMC, USB, PCI, cPCI, PCI-104, PCMCIA, PMC, PC/104, PC/104-
Plus, VME/VXI, and ISAbus cards. Our 1553 data bus board solutions are integral elements of military, aerospace,
and industrial applications. Our extensive line of military and space grade components provide MIL-STD-1553
interface solutions for microprocessors, PCI buses, and simple systems. Our 1553 data bus solutions are
designed into a global network of aircraft, helicopter, and missle programs.
ARINC 429
DDC also has a wide assortment of quality ARINC-429 commercial, military, and COTS grade cards and
components, which will meet your data conversion and data interface needs. DDC supplies ARINC-429 board
level products in a variety of form factors including AMC, USB, PCI, PMC, PCI-104, PC/104 Plus, and PCMCIA
boards. DDC's ARINC 429 components ensure the accurate and reliable transfer of flight-critical data. Our 429
interfaces support data bus development, validation, and the transfer of flight-critical data aboard commercial
aerospace platforms.
Fibre Channel
DDC has developed its line of high-speed Fibre Channel network access controllers and switches to support the
real-time processing demands of field-critical data networking between sensors, computer nodes, data storage,
displays, and weapons, for air, sea, and ground military vehicles. Fibre Channel's architecture is optimized to
meet the performance,reliability, and demanding environmental requirements of embedded, real time, military
applications, and designed to endure the multi-decade life cycle demands of military/aerospace programs.
DATA DEVICE CORPORATION
ULTRA-SMALL, ULTRA-LOW POWER MIL-STD-1553
SINGLE PACKAGE SOLUTION
BU-67301B DATA SHEET
The information provided in this Data Sheet is believed to be accurate; however, no
responsibility is assumed by Data Device Corporation for its use, and no license or rights
are granted by implication or otherwise connection therewith.
Specifications are subject to change without notice.
Please visit our Web site at
http://www.ddc-web.com/
for the latest information.
All rights reserved. No part of this Data Sheet may be reproduced or transmitted in any
form or by any mean, electronic, mechanical photocopying recording, or otherwise,
without the prior written permission of Data Device Corporation.
105 Wilbur Place
Bohemia, New York 11716-2426
Tel: (631) 567-5600, Fax: (631) 567-7358
World Wide Web -
http://www.ddc-web.com
For Technical Support -
1-800-DDC-5757 ext. 7771
United Kingdom -
Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
France -
Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany -
Tel: +49-(0)89-15 00 12-11, Fax: +49-(0)89-15 00 12-22
Japan -
Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
Asia -
Tel: +65-6489-4801
© 2010 Data Device Corp.
Data Device Corporation
www.ddc-web.com
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RECORD OF CHANGE
Revision
Pre Rev A
Rev. A
Date
Sept., 2010
Sept., 2011
Pages
All
All
Preliminary release
Initial Release
Description
Rev. B
Dec., 2011
6, 7, 9, 38, 113,
25-93, 95, 101-
115
Table 1: removed part numbers from Supply Voltage
section, changed Storage Temperature Max. from:
+150°C to: +125°C., added Ramp Rate specs, added
Junction Temperature (T
J
)
Table 7: Changed T
ah
min from 2ns to 7ns.
Table 25: removed redundant B1 listing in NC section.
Section 6: changed heading to Host Interface.
Added Section 7: Power Inputs
Tables 15 - 22: Added Pullup/Pulldown column and
values
Table 1: Eliminated reference to “(Hottest Die)”.
Figure 5: Eliminated “MT 100 µs Timer (16-bit)” block.
Added Figure 56, Timing of CLK_IN, Logic_V
DDIO
,
PLL_+1.8V, and Core_+1.8V.
Figure 58: Made corrections
Figure 59: Made corrections
Table 22: Changed second column signal description
for nSINGEND(I).
Figure 2: Added nPOR and PLL_LOCKED
Figures 7-10 and Figures 19-22: Added nPOR,
supervisor circuit, and PLL_LOCKED, modifed use of
nMSTCLR
Figure 48: Added nPOR and PLL_LOCKED
Paragraph 7.2: updated power-up sequence, modified
Figure 56
Table 15: Added nPOR and PLL_LOCKED
Table 18: Modified RST#
Table 19: Modified nMSTCLR
Table 26: Added nPOR and PLL_LOCKED
Figure 61: Added nPOR and PLL_LOCKED
Updated Figure 56
Figure 2: Corrected CH. A 1553 Stub designation
Tables 15 – 17: Adjusted column widths
Updated Table 1 and Figure 48
Rev. C
Dec., 2011
10, 15, 96-97, 99,
100, 115
Rev. D
January, 2012
7, 36-39, 55-58,
89. 96-98, 104,
107-108, 110,
122, 125
Rev. E
Rev. F
Rev. G
Feb., 2012
June, 2012
January, 2014
98
7, 104, 105
11, 89
Data Device Corporation
www.ddc-web.com
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TABLE OF CONTENTS
1
PREFACE............................................................................................................. 1
1.1
1.2
1.3
1.4
Text Usage.................................................................................................................. 1
Standard Definitions .................................................................................................... 1
Trademarks ................................................................................................................. 1
Technical Support ....................................................................................................... 2
2
OVERVIEW .......................................................................................................... 3
2.1
2.2
2.3
2.4
Features ...................................................................................................................... 3
Specifications .............................................................................................................. 8
Additional Support Documents .................................................................................. 12
Total-AceXtreme®
Development Kit .......................................................................... 13
3
4
MIL-STD-1553 MODES AND ARCHITECTURE ................................................ 15
3.1 Bus Controller Mode.................................................................................................. 15
GLOBAL FEATURES ........................................................................................ 22
4.1
4.2
4.3
4.4
Transceivers and Isolation Transformers................................................................... 22
Time Tags ................................................................................................................. 22
Local Timer ............................................................................................................... 22
DMA Controller.......................................................................................................... 23
5
BUILT-IN TEST .................................................................................................. 25
5.1
Total-AceXtreme®
Self-Test...................................................................................... 25
5.2 JTAG Boundary Scan................................................................................................ 25
6
HOST INTERFACE ............................................................................................ 27
6.1
6.2
6.3
6.4
6.5
Host Interface Configuration Options......................................................................... 27
Parallel CPU Interface ............................................................................................... 27
Asynchronous Interface Mode ................................................................................... 35
Synchronous Host Processor Interface ..................................................................... 51
PCI Interface ............................................................................................................. 88
7
POWER INPUTS ................................................................................................ 97
7.1 Decoupling Capacitors .............................................................................................. 97
7.2 Power Sequencing .................................................................................................... 97
8
MIL-STD-1553 TRANSCEIVER OPTIONS ...................................................... 100
8.1 Using the Internal Transceivers ............................................................................... 100
8.2 Using External Fiber Optic Transceivers ................................................................. 102
9
THERMAL MANAGEMENT FOR TOTAL-ACEXTREME ................................ 104
10 REGISTER AND MEMORY ADDRESSING ..................................................... 107
10.1 Memory Address Space .......................................................................................... 107
10.2 Register Address Space .......................................................................................... 107
Data Device Corporation
www.ddc-web.com
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