®
HSP45240
Address Sequencer
Description
The Intersil HSP45240 is a high speed Address Sequencer
which provides specialized addressing for functions like
FFTs, 1-D and 2-D filtering, matrix operations, and image
manipulation. The sequencer supports block oriented
addressing of large data sets up to 24-bits at clock speeds
up to 50MHz.
Specialized addressing requirements are met by using the
onboard 24 x 24 crosspoint switch. This feature allows the map-
ping of the 24 address bits at the output of the address genera-
tor to the 24 address outputs of the chip. As a result, bit reverse
addressing, such as that used in FFTs, is made possible.
A single chip solution to read/write addressing is also made
possible by configuring the HSP45240 as two 12-bit
sequencers. To compensate for system pipeline delay, a
programmable delay is provided on 12 of the address out-
puts.
The HSP45240 is manufactured using an advanced CMOS
process, and is a low power fully static design. The configu-
ration of the device is controlled through a standard micro-
processor interface and all inputs/outputs, with the exception
of clock, are TTL compatible.
July 2004
Features
• Block Oriented 24-Bit Sequencer
• Configurable as Two Independent 12-Bit Sequencers
• 24 x 24 Crosspoint Switch
• Programmable Delay on 12 Outputs
• Multi-Chip Synchronization Signals
• Standard
µP
Interface
• 100pF Drive on Outputs
• DC to 50MHz Clock Rate
Applications
• 1-D, 2-D Filtering
• Pan/Zoom Addressing
• FFT Processing
• Matrix Math Operations
Ordering Information
PART NUMBER
HSP45240JC-33
HSP45240JC-50
TEMP.
RANGE (°C)
0 to 70
0 to 70
PACKAGE
68 Ld PLCC
68 Ld PLCC
PKG.
DWG. #
N68.95
N68.95
Block Diagram
STARTOUT
ADDVAL
DONE
BLOCKDONE
12
REG
STARTIN
START
CIRCUITRY
SEQUENCE
GENERATOR
24
CROSSPOINT
SWITCH
OUT12-23
OEH
12
DELAY
1-8
OUT0-11
OEL
PROCESSOR INTERFACE
BUSY
DLYBLK
D0-6, CS, A0, WR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Harris Corporation 1997, Copyright Intersil Americas Inc. 2004. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
FN2489.4
HSP45240
Pinouts
ADDRESS SEQUENCER HSP45240
68 PIN PLASTIC LEADED CHIP CARRIER (PLCC)
GND
OUT23
OUT22
V
CC
OUT21
OUT20
GND
OUT19
OUT18
V
CC
OUT17
OUT16
GND
OUT15
OUT14
OUT13
NC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
NC
D0
D1
D2
D3
D4
D5
D6
GND
WR
A0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC
OEH
OEL
DLYBLK
STARTIN
STARTOUT
ADDVAL
V
CC
BUSY
BLOCKDONE
DONE
GND
OUT0
OUT1
V
CC
OUT2
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
OUT12
GND
OUT11
OUT10
V
CC
OUT9
OUT8
GND
OUT7
OUT6
V
CC
OUT5
OUT4
GND
OUT3
NC
CS
GND
CLK
V
CC
RST
NC
Pin Descriptions
PLCC
PIN
NUMBER
6, 24, 34, 41
49, 55, 68
3, 9, 18, 22,
38, 46, 52,
58, 65
25
+5V power supply pin.
NAME
V
CC
GND
TYPE
I
DESCRIPTION
I
GROUND.
RST
I
RESET: This active low input causes a chip reset which lasts for 26 clocks after RST
has been deasserted. The reset initializes the Crosspoint Switch and some of the con-
figuration registers as described in the Processor Interface Section. The chip must be
clocked for reset to complete.
CLOCK: The “CLK” signal is a CMOS input which provides the basic timing for address
generation.
WRITE: The rising edge of this input latches the data/address on D0-6 to be latched into
the Processor Interface.
CHIP SELECT: This active “low” input enables the configuration data/address on
D0-6 to be latched into the Processor Interface.
ADDRESS 0: This input defines D0-6 as a configuration register address if “high”, and
configuration data if “low”, (see Processor Interface text).
DATA BUS: Data bus for Processor Interface.
OUTPUT ENABLE HIGH: This asynchronous input is used to enable the output buffers
for OUT 12-23.
CLK
I
23
WR
I
19
CS
I
21
A0
I
20
D0-6
OEH
I
I
11-17
28
2
HSP45240
Pin Descriptions
PLCC
PIN
NUMBER
29
NAME
OEL
TYPE
I
DESCRIPTION
OUTPUT ENABLE LOW: This asynchronous input is used to enable the output buffers
for OUT0-11.
START-IN: This active low input initiates an addressing sequence. May be tied to
STARTOUT of another H5P45240 for multichip synchronization. STARTIN should only
be asserted for one CLK because address sequencing begins after STARTIN is deas-
serted.
DELAY BLOCK: This active “high” input may be used to halt address generation on ad-
dress block boundaries (see Sequence Generator text). The required timing relation-
ship of this signal to the end of an address block is shown in Application Note 9205.
OUTPUT BUS: TTL compatible 24-bit Address Sequencer output.
STARTIN
I
31
DLYBLK
I
30
OUT0-23
O
39, 40, 42, 45,
47, 48, 50, 51,
53, 54, 56, 57,
59, 62-64, 66,
67, 1, 2, 4, 5,
7, 8
36
BLOCK DONE
O
BLOCK DONE: This active low output signals when the last address in an address
block is on OUT0-23.
DONE: This active low output signals when the last address of an address sequence is
on OUT0-23.
ADDRESS VALID: This active low output signals when the first address of an address
sequence is on 0UT0-23.
START-OUT: This active low output is generated when an address sequence is initiat-
ed by a mechanism other than STARTIN. May be tied to the STARTIN of other
H5P45240’s for multichip synchronization.
BUSY: This active low output is asserted one CLK after RST is deasserted and will re-
main asserted for 25 CLK’s. While BUSY is asserted, all writes to the Processor Inter-
face are disabled.
DONE
O
37
ADDVAL
O
33
START-OUT
O
32
BUSY
O
35
NOTE: #Denotes active low.
3
HSP45240
Functional Description
The Address Sequencer is a 24-bit programmable address
generator. As shown in the Block Diagram, the sequencer
consists of 4 functional blocks: the start circuitry, the
sequence generator, the crosspoint switch, and the proces-
sor interface. The addresses produced by the sequence
generator are input into the crosspoint switch. The cross-
point switch maps 24 bits of address input to a 24-bit output.
This allows for addressing schemes like “bit-reverse”
addressing for FFT’s. A programmable delay block is pro-
vided to allow the MSW of the output to be skewed from the
LSW. This feature may be used to compensate for proces-
sor pipeline delay when the sequence generator is config-
ured as two independent 12-bit sequencers. Address
Sequencer operation is controlled by values loaded into con-
figuration registers associated with the sequence generator,
crosspoint switch, and start circuitry. The configuration regis-
ters are loaded through the processor interface.
As shown in Figure 1, the Sequence Generator is subdivided
into the address generation and control sections. The
address generation section performs an accumulation based
on the output of MUX1 and MUX2. The control section gov-
erns the operation of the multiplexers, enables loading of the
Block Start Address register, and signals completion of an
address sequence.
An address sequence is started when the control section of
the Sequence Generator receives the internal START signal
from the Start Circuitry. When the START signal is received,
the control section multiplexes the contents of the Start
Address Register and a “0” to the adder. The result of this
summation is the first address in the first block of the
address sequence. This value is stored in the Block Start
Address register by an enable generated from the control
section, and the multiplexers are switched to feed the output
of the Holding and Address Increment registers to the adder.
Address generation will continue with the Address Increment
added to the contents of the Holding Register until the first
address block has been completed.
An address block is completed when the number of
addresses generated since the beginning of the address
block equals the value stored in the Block Size register.
When the last address of the block is generated, BLOCK-
DONE is asserted to signal the end of the address block
(see Application Note 9205). On the following CLK, the mul-
tiplexers are configured to pass the contents of the Block
Start Address and Block Increment registers to the adder
which generates the first address of the next address block.
An enable from the control section allows this value to
update the Block Start Address register, and the multiplexers
are switched to feed the Holding and Address Increment
registers to the adder for generation of the remaining
addresses in the block.
The address sequence is completed when the number of
address blocks generated equals the value loaded into the
Number of Blocks register. When the final address in the last
address block has been generated, DONE and BLOCK-
DONE are asserted to signal the completion of the address
sequence.
The parameters governing address generation are loaded
into five 24-bit configuration registers via the Processor
Interface. These parameters include the Start Address, the
beginning address of the sequence; the Block Size, the
number of addresses in the address block; the Address
Increment, the increment between addresses in a block; the
Number of Blocks, the number of address blocks in a
sequence (minimum 1); the Block Increment, the increment
between starting addresses of each block. The loading and
structure of these registers is detailed in the Processor Inter-
face text.
Start Circuitry
The Start Circuitry generates the internal START signal
which causes the Sequence Generator to initiate an
addressing sequence. The START signal is produced by
writing the Processor Interface’s “Sequencer Start” address
(see Processor Interface text), by asserting the STARTlN
input, or by the terminal address of a sequence generated
under “One-Shot Mode with Restart” (see Sequence Gener-
ator Section). Care should be taken to assert STARTlN for
only one clock cycle to ensure proper operation. A program-
mable delay from 1 to 31 clocks is provided to delay the initi-
ation of an addressing sequence by delaying the internal
START signal (see Processor Interface text).
The Start Circuitry generates the output signal ADDVAL
which is asserted when the first valid output address is at the
pads. In addition, the Start Circuitry generates the
“STARTOUT” signal for multichip synchronization. Note:
STARTOUT is only generated when an addressing
sequence is started by writing the “Sequencer Start” address
of the Processor Interface, or an internal START is gener-
ated by reaching the end of an addressing sequence pro-
duced by “One-Shot Mode with Restart”.
Sequence Generator
The Sequence Generator is a block oriented address gener-
ator. This means that the desired address sequence is sub-
divided into one or more address blocks, each containing a
user defined number of addresses. User supplied configura-
tion data determines the number of address blocks and the
characteristics of the address sequence to be generated.
4
HSP45240
CURRENT
BLOCK
START
ADDRESS
R
E
G
R
E
G
R
E
G
R
E
G
“0”
M
U
X
1
“0”
12 MSB
A
D
D
E
R
M
U
X
12 LSB
HOLDING
REGISTER
12
R
E
G
24
TO
CROSS-
POINT
SWITCH
STEP SIZE
START
ADDRESS
BLOCK
STEP SIZE
M
U
X
2
12
ADDRESS
GENERATION
TEST MODE
DATA
MUX CONTROLS/
REGISTER ENABLES
CONTROL
BLOCK
SIZE
R
E
G
R
E
G
R
E
G
DONE
NUMBER
OF
BLOCKS
SEQUENCE
GENERATOR
CONTROL
BLOCKDONE
DLYBLK
MODE
“START”
FIGURE 1. SEQUENCE GENERATOR BLOCK
Three modes of operation may be selected by loading the 6-bit
Mode Control register (see Processor Interface). The three
modes of operation are:
1. One-Shot Mode without Restart Address generation halts
after completion of the user specified address sequence.
Address generation will not resume until the internal
START signal is generated by the Start Circuitry. When the
final address in the final block of the address sequence is
generated, both DONE and BLOCKDONE are asserted
and the last address is held on OUT0-23 (See Application
Note 9205).
2. One-Shot Mode with Restart: This mode is identical to
One-Shot Mode without Restart with the exception that the
Start Circuitry automatically generates an internal START
at the end of the user specified sequence to restart ad-
dress generation. The end of the address sequence is sig-
naled by the assertion of DONE, BLOCKDONE, and
STARTOUT as shown in Application Note 9205. In this
mode, the first address of the next sequence immediately
follows the last address of the current sequence if start de-
lay is disabled.
3. Continuous Mode: Address generation never terminates.
Address generation proceeds based on the Start Address,
Address Increment, Block Size, and Block Increment Pa-
rameters. The Number of Blocks parameter is ignored,
and the DONE signal is never asserted.
The Mode Control register is also used to configure the
Sequence Generator for operation as two independent 12-bit
address sequencers. In dual sequencer mode, the adder in
the sequence generator suppresses the carry from the 12
LSBs to the 12 MSBs. With the carry suppressed, two inde-
pendent sequences may be produced. These 12-bit address
sequences may be delayed relative to each other by program-
ming the Mode Control register for a delay up to 7 clocks. This
feature is useful to compensate for pipeline delay when using
dual sequencer mode to generate read/write addressing.
The DLYBLK input can be used to halt address generation at
the end of any address block within a sequence. In addition,
DLYBLK can be used to delay an address sequence from
restarting if asserted at the end of the final address block gen-
erated under “One-Shot Mode with Restart”. See Application
Note 9205 for the timing relationship of DLYBLK to the end of
the address block required to halt address sequencing.
Crosspoint Switch
The crosspoint switch is responsible for reordering the
address bits output by the sequence generator. The switch
allows any of its 24 inputs to be independently connected to
any of its 24 outputs. The crosspoint switch outputs can be
driven by only one input, however, one input can drive any
number of switch outputs. If none of the inputs are mapped to
a particular output bit, that output will be “low”.
The input to output map is configured through the processor
interface. The I/O map is stored in a bank of 24 configuration
registers. Each register corresponds to one output bit. The
output bit is mapped to the input via a value, 0 to 23, stored in
the register. After power-up, the user has the option of config-
uring the switch in 1:1 mode by using the reset input, “RST”.
In 1:1 mode the crosspoint switch outputs are in the same
order as the input. More details on configuring the switch reg-
isters are contained in the Processor Interface text.
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