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HSP45116_04: 产品描述16-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP160; 产品类别半导体嵌入式处理器和控制器; 文件大小264KB，共16页; 制造商Intersil ( Renesas ); 官网地址http://www.intersil.com/cda/home/

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HSP45116_04概述

16-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP160

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HSP45116

Data Sheet

July 2004

FN2485.8

Numerically Controlled

Oscillator/Modulator

The Intersil HSP45116 combines a high performance

quadrature Numerically Controlled Oscillator (NCO) and a

high speed 16-bit Complex Multiplier/Accumulator (CMAC)

on a single IC. This combination of functions allows a

complex vector to be multiplied by the internally generated

(cos, sin) vector for quadrature modulation and

demodulation. As shown in the Block Diagram, the

HSP45116 is divided into three main sections. The

Phase/Frequency Control Section (PFCS) and the

Sine/Cosine Section together form a complex NCO. The

CMAC multiplies the output of the Sine/ Cosine Section with

an external complex vector.

The inputs to the Phase/Frequency Control Section consist

of a microprocessor interface and individual control lines.

The phase resolution of the PFCS is 32 bits, which results in

frequency resolution better than 0.008Hz at 33MHz. The

output of the PFCS is the argument of the sine and cosine.

The spurious free dynamic range of the complex sinusoid is

greater than 90dBc.

The output vector from the Sine/Cosine Section is one of the

inputs to the Complex Multiplier/Accumulator. The CMAC

multiplies this (cos, sin) vector by an external complex vector

and can accumulate the result. The resulting complex vectors

are available through two 20-bit output ports which maintain

the 90dB spectral purity. This result can be accumulated

internally to implement an accumulate and dump filter.

A quadrature down converter can be implemented by

loading a center frequency into the Phase/Frequency

Control Section. The signal to be down converted is the

Vector Input of the CMAC, which multiplies the data by the

rotating vector from the Sine/Cosine Section. The resulting

complex output is the down converted signal.

Features

• NCO and CMAC on One Chip

• 15MHz, 25.6MHz, 33MHz Versions

• 32-Bit Frequency Control

• 16-Bit Phase Modulation

• 16-Bit CMAC

• 0.008Hz Tuning Resolution at 33MHz

• Spurious Frequency Components < -90dBc

• Fully Static CMOS

Applications

• Frequency Synthesis

• Modulation - AM, FM, PSK, FSK, QAM

• Demodulation, PLL

• Phase Shifter

• Polar to Cartesian Conversions

Ordering Information

PART NUMBER

HSP45116VC-25

HSP45116AVC-52

TEMP.

RANGE (°C)

0 to 70

PACKAGE

PKG.

DWG. #

160 Ld MQFP Q160.28x28

†

This part has its own data sheet under HSP45116A,

Document # FN4156.

Block Diagram

VECTOR INPUT

SINE/

COSINE

ARGUMENT

MICROPROCESSOR

INTERFACE

INDIVIDUAL

CONTROL SIGNALS

PHASE/

FREQUENCY

CONTROL

SECTION

SIN

SINE/

COSINE

SECTION

COS

CMAC

VECTOR OUTPUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

HSP45116

Pin Description

NAME

GND

C0-15

AD0-1

CLK

ENPHREG

ENOFREG

ENCFREG

ENPHAC

ENTIREG

NUMBER

A1, A9, A15, G1,

J15, Q1, Q7, Q15

A8, A14, B1, H1,

H15, P15, Q2, Q8

N8-11, P8-13,

Q9-14

N7, P7

TYPE

+5V Power supply input.

Power supply ground input.

Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.

Address pins for selecting destination of C0-15 data.

Chip Select (active low).

Write Enable. Data is clocked into the register selected by AD0-1 on the rising edge of WR when

the CS line is low.

Clock. All registers, except the control registers clocked with WR, are clocked (when enabled)

by the rising edge of CLK.

Phase Register Enable (active low). Registered on chip by CLK. When active, after being

clocked onto chip, ENPHREG enables the clocking of data into the phase register.

Frequency Offset Register Enable (active Low). Registered on chip by CLK. When active, after

being clocked onto chip, ENOFREG enables clocking of data into the frequency offset register.

Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after

being clocked onto chip, ENCFREG enables clocking of data into the center frequency register.

Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after

being clocked onto chip, ENPHAC enables clocking of the phase accumulator register.

Time Interval Control Register Enable (active low). Registered on chip by CLK. When active,

after being clocked onto chip, ENTIREG enables clocking of data into the time accumulator

Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by

CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and

imaginary input data register.

Modulo

π/2π

Select. When low, the Sine and Cosine ROMs are addressed modulo 2π (360

degrees). When high, the most significant address bit is held low so that the ROMs are

addressed modulo

(180 degrees). This input is registered on chip by clock.

Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,

after being clocked onto chip, CLROFR zeros the data path from the frequency offset register to

the frequency adder. New data can still be clocked into the frequency offset register; CLROFR

does not affect the contents of the register.

Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback

path in the phase accumulator without clearing the phase accumulator register.

External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90,

180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of

the phase control path are set to zero.

These bits are loaded into the phase register when ENPHREG is low.

PMSEL

Phase Modulation Select Line. This line determines the source of the data clocked into the phase

(MOD0-1) are selected for the most significant two bits and the least significant two bits and the

least significant 14 bits are set to zero. This control is registered by CLK.

ROM Bypass, Timer Load. Active low, registered by CLK. This input bypasses the sine/ cosine

ROM so that the 16-bit phase adder output and lower 16 bits of the phase accumulator go

directly to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the timer

accumulator register by zeroing the feedback in the accumulator.

Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to

increment by one, in addition to the values in the phase accumulator register and frequency

adder.

DESCRIPTION

ENI

MODPI/2PI

CLROFR

LOAD

MOD0-1

M3, N3

RBYTILD

PACI

HSP45116

Pin Description

NAME

PACO

(Continued)

TYPE

DESCRIPTION

Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output

indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has

been reached.

Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low

when a carry is generated by the time interval accumulator. This function is provided to time out

control events such as synchronizing register clocking to data timing.

Real Input Data Bus. This is the external real component into the complex multiplier. The bus is

clocked into the real input data register by CLK when ENI is asserted; two’s complement.

NUMBER

L13

TICO

RIN0-18

C1, C2, D1, D2, E1-

3, F1-3, G2, G3,

H2, H3, J1-3, K1,

A2-7, B2-7, C3-8,

K3, L1

IMIN0-18

Imaginary Input Data Bus. This is the external imaginary component into the complex multiplier.

The bus is clocked into the real input data register by CLK when ENI is asserted; two’s

complement.

Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the

complex multiplier. The shift controls are common to the shifters on both of the busses.

Accumulate/Dump Control. This input controls the complex accumulators and their holding

registers. When high, the accumulators accumulate and the holding registers are disabled.

When low, the feedback in the accumulators is zeroed to cause the accumulators to load.

The holding registers are enabled to clock in the results of the accumulation. This input is

registered by CLK.

SH0-1

ACC

BINFMT

This input is used to convert the two’s complement output to offset binary (unsigned) for

applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal

two’s complement representation. This input is registered by CLK.

This input enables the peak detect feature of the block floating point detector. When high, the

maximum bit growth in the output holding registers is encoded and output on the DET0-1 pins.

When the PEAK input is asserted, the block floating point detector output will track the maximum

growth in the holding registers, including the data in the holding registers at the time that PEAK

is activated.

These inputs select the data to be output on RO0-19 and IO0-19.

Real Output Data Bus. These Three-state outputs are controlled by OER and OEREXT.

OUTMUX0-1 select the data output on the bus.

PEAK

OUTMUX0-1

RO0-19

N12, N13

C15, D14, D15,

E14, E15, F13-15,

G13-15, H13, H14,

J13, J14, K13-15,

L15, M15

A10-13, B8-15, C9-

14, D13, E13

N15, L14

IO0-19

DET0-1

Imaginary Output Data Bus. These Three-state outputs are controlled by OEI and OEIEXT.

OUTMUX0-1 select the data output on the bus.

These output pins indicate the number of bits of growth in the accumulators. While PEAK is low,

these pins indicate the peak growth. The detector examines bits 15-18, real and imaginary

accumulator holding registers and bits 30-33 of the real and imaginary CMAC holding registers.

The bits indicate the largest growth of the four registers.

Three-state control for bits RO0-15. Outputs are enabled when the line is low.

Three-state control for bits RO16-19. Outputs are enabled when the line is low.

Three-state control for bits IO0-15. Outputs are enabled when the line is low.

Three-state control for bits IO16-19. Outputs are enabled when the line is low.

OER

OEREXT

OEI

OEIEXT

P14

M13

M14

N14

HSP45116_04相似产品对比

	HSP45116_04	HSP45116	HSP45116VC-25
描述	16-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP160	16-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP160	16-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP160

HSP45116_04

HSP45116_04概述

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