®
HSP45106
Data Sheet
July 2004
FN2809.7
16-Bit Numerically Controlled Oscillator
The Intersil HSP45106 is a high performance 16-bit
quadrature Numerically Controlled Oscillator (NCO16). The
NCO16 simplifies applications requiring frequency and
phase agility such as frequency-hopped modems, PSK
modems, spread spectrum communications, and precision
signal generators. As shown in the block diagram, the
HSP45106 is divided into a Phase / Frequency Control
Section (PFCS) and a Sine/Cosine Section.
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The frequency resolution is 32 bits, which provides for
resolution of better than 0.008Hz at 33MHz. User
programmable center frequency and offset frequency
registers give the user the capability to perform phase
coherent switching between two sinusoids of different
frequencies. Further, a programmable phase control register
allows for phase control of better than 0.006
o
. In applications
requiring up to 8-level PSK, three discrete inputs are
provided to simplify implementation.
The output of the PFCS is a 28-bit phase which is input to
the Sine/Cosine Section for conversion into sinusoidal
amplitude. The outputs of the Sine/Cosine Section are two
16-bit quadrature signals. The spurious free dynamic range
of this complex vector is greater than 90dBc.
For added flexibility when using the NCO16 in conjunction
with DACs, a choice of either parallel or serial outputs with
either two’s complement or offset binary encoding is
provided. In addition, a synchronization signal is available
which indicates serial word boundaries.
Features
• 25.6MHz, 33MHz Versions
• 32-Bit Center and Offset Frequency Control
• 16-Bit Phase Control
• 8 Level PSK Supported Through Three Pin Interface
• Simultaneous 16-Bit Sine and Cosine Outputs
• Output in Two’s Complement or Offset Binary
• <0.008Hz Tuning Resolution at 33MHz
• Serial or Parallel Outputs
• Spurious Frequency Components <-90dBc
• 16-Bit Microprocessor Compatible Control Interface
Applications
• Direct Digital Synthesis
• Quadrature Signal Generation
• Spread Spectrum Communications
• PSK Modems
• Modulation - FM, FSK, PSK (BPSK, QPSK, 8PSK)
• Frequency Hopping Communications
• Precision Signal Generation
• Related Products
- Use with Data Acquisition Parts HI5731 or HI5741
Ordering Information
PART NUMBER
HSP45106JC-25
HSP45106JC-33
TEMP.
RANGE (°C)
0 to 70
0 to 70
PACKAGE
84 Ld PLCC
84 Ld PLCC
PKG.
DWG. #
N84.1.15
N84.1.15
Block Diagram
MICROPROCESSOR
INTERFACE
CLOCK
DISCRETE
CONTROL SIGNALS
SIN/COS
ARGUMENT
32
PHASE/
FREQUENCY
CONTROL
SECTION
SINE/
COSINE
SECTION
SINE
16
COSINE 16
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HSP45106
Pinouts
84 LEAD PLCC
TOP VIEW
C0
C1
C2
C3
C4
C5
C6
V
CC
C7
C8
C9
C10
C11
C12
C13
C14
C15
GND
A0
A1
A2
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
TICO
COS15
COS14
COS13
GND
COS12
COS11
COS10
COS9
COS8
COS7
COS6
COS5
COS4
V
CC
COS3
COS2
COS1
COS0
OEC
DACSTRB
PMSEL
MOD0
MOD1
MOD2
TEST
V
CC
WR
GND
CS
ENCFREG
ENOFREG
INHOFR
ENTIREG
INITTAC
ENPOREG
INPHAC
PACI
INITPAC
BINFMT
PAR/SER
V
CC
Pin Descriptions
NAME
V
CC
GND
C(15:0)
A(2:0)
CS
WR
CLK
ENPOREG
I
I
I
I
I
I
TYPE
+5 power supply pin.
Ground.
Control input bus for loading phase, frequency, and timer data into the PFCS. C0 is LSB.
Address pins for selecting destination of C(15:0) data (Table 2). A0 is the LSB
Chip select (active low). Enables data to be written into Control Registers by WR.
Write enable (active low). Data is clocked into the register selected by A(2:0) on the rising edge of WR when CS
is low.
Clock. All registers, except the Control Registers clocked with WR, are clocked (when enabled) by the rising edge
of CLK.
Phase Offset Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip,
ENPOREG enables the clocking of data into the Phase Offset Register. Allows ROM address to be updated
regardless of ENPHAC.
Offset Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENOFREG enables the clocking of data into the Offset Frequency Register.
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENCFREG enables the clocking of data into the Center Frequency Register.
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENPHAC enables the clocking of data into the Phase Accumulator Register.
Timer Increment Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENTIREG enables the clocking of data into the Timer Increment Register.
Inhibit Offset Frequency Register Output (active low). Registered on chip by CLK. When active, after being
clocked onto chip, INHOFR zeroes the data path from the Offset Frequency Register to the Frequency Adder. New
data can be still clocked into the Offset Frequency Register. INHOFR does not affect the contents of the register.
Initialize Phase Accumulator (active low). Registered on chip by CLK. Zeroes the feedback path in the Phase
Accumulator. Does not clear the Phase Accumulator Register.
Modulation Control Inputs. When selected with the PMSEL line, these bits add an offset of 0, 45, 90, 135, 180,
225, 270, or 315 degrees to the current phase (i.e., modulate the output). The lower 13 bits of the phase control
are set to zero. These bits are registered when the Phase Offset Register is enabled.
DESCRIPTION
ENOFREG
ENCFREG
ENPHAC
ENTIREG
INHOFR
I
I
I
I
I
INITPAC
MOD(2:0)
I
I
2
OES
SIN15
SIN14
SIN13
GND
SIN12
SIN11
SIN10
SIN9
SIN8
SIN7
SIN6
SIN5
V
CC
SIN4
SIN3
SIN2
SIN1
SIN0
CLK
GND
HSP45106
Pin Descriptions
NAME
PMSEL
TYPE
I
(Continued)
DESCRIPTION
Phase Modulation Select input. Registered on chip by CLK. This input determines the source of the data clocked
into the Phase Offset Register. When high, the Phase Input Register is selected. When low, the external
modulation pins (MOD(2:1)) control the three most significant bits of the Phase Offset Register and the 13 least
significant bits are set to zero.
Phase Accumulator Carry Input (active low). Registered on chip by CLK.
Initialize Timer Accumulator (active low). This input is registered on chip by CLK. When active, after being clocked
onto chip, INITTAC enables the clocking of data into the Timer increment Register, and also zeroes the feedback
path in the Timer Accumulator.
Test Select Input. Registered on chip by CLK. This input is active high. When active, this input enables test busses
to the outputs instead of the sine and cosine data.
Parallel/Serial Output Select. This input is registered on chip by CLK. When low, the sine and cosine outputs are
in serial mode. The Output Shift Registers will load in new data after ENPHAC goes low and will start shifting the
data out after ENPHAC goes high. When this input is high, the Output Registers are loaded every clock and no
shifting takes place.
Format. This input is registered on chip by CLK. When low, the MSB of the SIN and COS are inverted to form an
offset binary (unsigned) number.
Three-state control for bits SIN(15:0). Outputs are enabled when OES is low.
Three-state control for bits COS(15:0). Outputs are enabled when OEC is low.
Timer Accumulator Carry Output. Active low, registered. This output goes low when a carry is generated by the
Timer Accumulator.
DAC Strobe (active low). In serial mode, this output will go low when the first bit of a new output word is valid at
the shift register output. This pin is active only in serial mode.
Sine Output Data. When parallel mode is enabled, data is output on SIN(15:0). When serial mode is enabled,
output data bits are shifted out of SIN15 and SIN0. The bit stream on SIN15 is provided MSB first while the bit
stream on SIN0 is provided LSB first.
Cosine Output Data. When parallel mode is enabled, data is output on COS(15:0). When serial mode is enabled,
output data bits are shifted out of COS15 and COS0. The bit stream on COS15 is provided MSB first while the bit
stream in COS0 is provided LSB first.
Used to align chip in socket or on circuit board. Must be left as a no connect in circuit. (CPGA Package only).
PACI
INITTAC
I
I
TEST
PAR/SER
I
I
BINFMT
OES
OEC
TICO
DACSTRB
SIN(15:0)
I
I
I
O
O
O
COS(15:0)
O
Index Pin
Functional Description
The 16-bit Numerically Controlled Oscillator (NCO16)
produces a digital complex sinusoid waveform whose
frequency and phase are controlled through a standard
microprocessor interface and discrete inputs. The NCO16
generates 16-bit sine and cosine vectors at a maximum
sample rate of 33MHz. The NCO16 can be preprogrammed
to produce a constant (CW) sine and cosine output for Direct
Digital Synthesis (DDS) applications. Alternatively, the
phase and frequency inputs can be updated in real time to
produce a FM, PSK, FSK, or MSK modulated waveform. To
simplify PSK generation, a 3 pin interface is provided to
support modulation of up to 8 levels.
As shown in Figure 1, the HSP45106 Block Diagram, the
NCO16 is comprised of a Phase and Frequency Control
Section (PFCS) and Sine/ Cosine Section. The PFCS stores
the phase and frequency control inputs and uses them to
calculate the phase angle of a rotating complex vector. The
Sine/Cosine Section performs a lookup on this phase and
generates the appropriate amplitude values for the sine and
cosine. These quadrature outputs may be configured as
serial or parallel with either two's complement or offset
binary format.
Phase/Frequency Control Section
The phase and frequency of the quadrature outputs are
controlled by the PFCS (Figure 1). The PFCS generates a
32-bit word which represents the instantaneous phase
(Sin/Cos argument) of the sine and cosine waves being
generated. This phase is incremented on the rising edge of
each CLK by the preprogrammed amounts in the phase and
Frequency Control Registers. As the instantaneous phase
steps from 0 through full scale (2
32
- 1), the phase of the
quadrature outputs proceeds from 0
o
around the unit circle
counter clockwise.
The PFCS is comprised of a Phase Accumulator Section,
Phase Offset adder, Input Section, and a Timer Accumulator
Section. The Phase Accumulator computes the
instantaneous phase angle from user programmed values in
the Center and Offset Frequency Registers. This angle is
then fed into the Phase Offset adder where it is offset by the
preprogrammed value in the Phase Offset Register. The Input
Section routes data from a microprocessor compatible control
bus and discrete input signals into the appropriate configuration
registers. The Timer Accumulator supplies a pulse to mark the
passage of a user programmed period of time.
3
OES
OEC
/
20
/
ADDRESS
DECODE
/
SIN/COS ARGUMENT
16
PHASE INPUT
PHASE
INPUT REG (16)
16
13
'0'
16
R.PMSEL
CENTER
FREQUENCY
FREQUENCY
ADDER
32
32
32
R
E
G
CLK
32
1
32
MUX
32
0
'0'
32
MUX
0
A
D
D
E
R
>
32
16
CLK >
R.ENCFREG
A
D
D
E
R
1
R
E
G
CENTER
FREQUENCY
32 REGISTER
0
MUX
ENCODER
R
E
G
MSB CENTER
FREQUENCY INPUT
REG (16)
16
R
E
G
LSB
CENTER
FREQUENCY
INPUT REG (16)
3
1
16 SIN
FORMAT
CONTROL 28
/
DACSTRB
SIN/COS
ROM
/
/
OUTPUT
CONTROL
16 COS
16
COS(15:0)
16
SIN(15:0)
R.ENPHAC
TEST
3
PAR/SER
BINFMT
INPUT SECTION (DISCRETE CONTROL INPUT SIGNALS
AND PROCESSOR CONTROL INTERFACE)
C(15:0)
1
0
INHOFR
R.INHOFR
MUX
4
>
MSB OFFSET
FREQUENCY INPUT
REG (16)
16
R
E
G
LSB OFFSET
FREQUENCY
INPUT REG (16)
16
OFFSET FREQUENCY
REGISTER
OFFSET
32
R
FREQUENCY 32
E
32
G
CLK >
'0'
R.ENOFREG
R.INHOFR
R.INITPAC
16
LSB TIMER
INCREMENT INPUT
REG (16)
R.PACI
R.ENPHAC
TIMER
INCREMENT 32
R
E
G
>
TIMER
INCREMENT CLK
REGISTER
R.ENTIREG
R.INITTAC
32
32
32
'0'
32
32
R
E
G
CLK
>
R
E
G
A
D
D
E
R
CLK
TIMER
ACCUMULATOR
SECTION
R.INITTAC
MOD(2:1)
WR
>
R
E
G
PHEN
28
R
E
G
WR
PHEN
CS
MSCFEN
WR
>
PHASE OFFSET
PHASE OFFSET
ADDER
REGISTER
16
16
A
R
16
D
E
D
16
G
E LSBs 16
CLK >
R
MSBs
CLK
R.ENPOREG
A(2:0)
D
E
C
O
D
E
LSCFEN
MSOFEN
LSOFEN
MSTIEN
WR >
LSCFEN
LSTIEN
WR
>
R
E
G
HSP45106
WR
LSOFEN
>
PHASE
ACCUMULATOR
REGISTER
PHASE
ACCUMULATOR
SECTION
WR >
MSTIEN
R
E
G
MSB TIMER INCREMENT
INPUT REG (16)
WR
LSTIEN
>
PMSEL
R.PMSEL
32
ENCFREG
R.ENCFREG
ENPOREG
R.ENPOREG
ENOFREG
R.ENOFREG
INITPAC
PACI
R
E
G
R.INITPAC
>
R
E
G
TICO
R.PACI
ENPHAC
R.ENPHAC
ENTIREG
R.ENTIREG
INITTAC
R.INITTAC
CLK
>
CLK
FIGURE 1. BLOCK DIAGRAM OF THE HSP45106
HSP45106
Input Section
The Input Section loads the data on C(15:0) into one of the
seven input registers, the LSB and MSB Center Frequency
Input Registers, the LSB and MSB Offset Frequency
Registers, the LSB and MSB Timer Input Registers, and the
Phase Input Register. The destination depends on the state of
A(2:0) when CS and WR are low (Table 1).
TABLE 1. ADDRESS DECODE MAPPING
MOD(2:0) DECODING
A2
0
0
0
0
1
1
1
1
X
A1
0
0
1
1
0
0
1
1
X
A0
0
1
0
1
0
1
0
1
X
CS
0
0
0
0
0
0
0
0
1
WR
↑
↑
↑
↑
↑
↑
↑
↑
X
FUNCTION
Load least significant bits of
Center Frequency input.
Load most significant bits of
Center Frequency input.
Load least significant bits of
Offset Frequency input.
Load most significant bits of
Offset Frequency input.
Load least significant bits of
Timing Interval input.
Load most significant bits of
Timing Interval input.
Load Phase Register
Reserved
Input Disabled
The number of steps required for this transition depends on
the phase increment calculated by the frequency adder. For
example, if the Center and Offset Frequency Registers are
programmed such that the output of the Frequency Adder is
4000 0000 hex, the Phase Accumulator will step the phase
from 0 to 360 degrees every 4 clock cycles. Thus, for a
30MHz CLK, the quadrature outputs will have a frequency of
30/4 MHz or 7.5MHz. In general, the frequency of the
quadrature output is determined by:
F
LO
=
(
N
×
f
CLK
⁄
2
32
),
or
(EQ. 1)
f
OUT
32
N
=
INT
-------------
2
,
f
CLK
(EQ. 2)
where N is the 32 bits of frequency control word that is
programmed. INT[•] is the integer of the computation. For
example, if the control word is 20000000 hexadecimal and the
clock frequency is 30MHz, then the output frequency would
be f
CLK
/8, or 3.75MHz.
The Frequency Adder sums the contents of both the Center
and Offset Frequency Registers to produce a phase
increment. By enabling INHOFR, the output of the Offset
Frequency Register is disabled so that the output frequency is
determined from the Center Frequency Register alone. For
BFSK modems, INHOFR can be asserted/ de-asserted to
toggle the quadrature outputs between two programmed
frequencies.
NOTE: Enabling/disabling INHOFR preserves
the contents of the Offset Frequency Register.
The Block Diagram shown in Figure 2 illustrates the method of
reading the phase accumulator of the NCO16 from a
microprocessor. The setup shown is very similar to that used
when the part is used for generating a complex sinusoid,
except that the internal SIN/COS lookup is bypassed by
setting the TEST pin to a logic 1(high). While the TEST pin is
high, the phase accumulator continues to drive the inputs of
the SIN/COS Generator while the most significant 28 bits of
the phase accumulator are multiplexed out onto the output
pins. Because of this, the part can be operated in two modes,
one where the SIN/COS Generator is permanently bypassed,
and one where the phase accumulator output is brought out to
the outputs as a check.
Figure 2 illustrates a circuit for reading out the phase
accumulator all the time. In this case, a microprocessor loads
the frequency and phase registers of the NCO16. This is fairly
straightforward, except for the Start Logic Block, which needs
to be synchronous to the oscillator clock and the
microprocessor interface. This has been left as an undefined
function, since it is dependent on the implementation. Also
note that all COS outputs (COS(15:0)) are connected,
although only COS(15:4) are valid in this application. The
microprocessor reads the sine and cosine data busses as if
they were RAMs, using the decoded address bus to select
one or the other.
Once the Input Registers have been loaded, the control inputs
ENCFREG, ENOFREG, ENTIREG, ENCTIREG, and
ENPOREG will allow the Input Registers to be downloaded to
the PFCS Control Registers with the input CLK. The control
inputs are latched on the rising edge of CLK and the Control
Registers are updated on the rising edge of the following CLK.
For example, to load the Center Frequency Register, the data
is loaded into the LSB and MSB Center Frequency Input
Register, and ENCFREG is set to zero; the next rising edge of
CLK will pass the registered version of ENCFREG,
R.ENCFREG, to the clock enable of the Center Frequency
Register; this register then gets loaded on the following rising
edge of CLK. The contents of the Input Registers are
downloaded to the Control Registers every clock, if the control
inputs are enabled.
Phase Accumulator Section
The Phase Accumulator adds the 32-bit output of the
Frequency Adder with the contents of a 32-bit Phase
Accumulator Register on every clock cycle. When the sum
causes the adder to overflow, the accumulation continues with
the least significant 32 bits of the result.
Initializing the Phase Accumulator Register is done by putting
a low on the INITPAC and ENPHAC lines. This zeroes the
feedback path to the accumulator, so that the register is
loaded with the current value of the Frequency Adder on the
next clock.
The frequency of the quadrature outputs is based on the
number of clock cycles required to step from 0 to full scale.
5
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