WCMA2016U4X
WCMA2016U4X
128K x 16 Static RAM
Features
• Low Voltage range:
— 2.7V-3.3V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1MHz
•
•
•
•
— Typical active current: 7 mA @ f = f
max
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
more than 99% when deselected (CE HIGH or both BLE and
BHE are HIGH). The input/output pins (I/O
0
through I/O
15
) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High En-
able and Byte Low Enable are disabled (BHE, BLE HIGH), or
during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The WCMA2016U4X is available in a 48-ball FBGA package.
Functional Description
The WCMA2016U4X is a high-performance CMOS static
RAMs organized as 128K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This device is ideal for portable applications such as cel-
lular telephones. The devices also have an automatic pow-
er-down feature that significantly reduces power consumption
by 80% when addresses are not toggling. The device can also
be put into standby mode reducing power consumption by
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
10
ROW DECODER
128K x 16
RAM Array
2048 x 1024
SENSE AMPS
I/O
0
– I/O
7
I/O
8
– I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
BHE
BLE
A
11
Pow
-
er Down
Circuit
A
12
A
13
A
14
A
15
A
16
WCMA2016U4X
Pin Configuration
[1, 2]
FBGA (Top View)
4
2
5
3
OE
BHE
I/O
10
I/O
11
A
0
A
3
A
5
NC
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
6
NC
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
I/O
12
DNU
I/O
13
NC
A
8
A
14
A
12
A
9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ...–0.5V to V
ccmax
+ 0.5V
DC Voltage Applied to Outputs
in High Z State
[3]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
.................................-0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Device
WCMA2016U4X
Range
Industrial
Ambient
Temperature
V
CC
–40°C to +85°C 2.7V to 3.3V
Product Portfolio
Power Dissipation (Industrial)
Product
V
CC
Range
V
CC(min.)
V
CC(typ.)
[4]
V
CC(max.)
WCMA2016U4X
2.7V
3.0V
3.3V
70 ns
Speed
Operating, I
CC
f = 1 MHz
Typ.
[4]
1 mA
Max.
2 mA
f = f
max
Typ.
[4]
7 mA
Max.
15 mA
Standby (I
SB2
)
Typ.
[4]
1
µA
Max.
15
µA
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or Vss to ensure proper application.
3. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
2
WCMA2016U4X
Electrical Characteristics
Over the Operating Range
WCMA2016U4X
Param-
eter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Cur-
rent
Output Leakage Cur-
rent
V
CC
Operating Supply
Current
Automatic CE
Power-Down Cur-
rent— CMOS Inputs
Automatic CE
Power-Down Cur-
rent— CMOS Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
V
CC
= 3.6V
I
OUT
= 0 mA
CMOS Levels
Test Conditions
I
OH
= –1.0 mA
I
OL
= 2.1mA
V
CC
= 2.7V
V
CC
= 2.7V
2.2
–0.3
–1
–1
7
1
Min.
2.4
0.4
V
CC
+ 0.5V
0.8
+1
+1
15
2
100
1
15
µA
mA
Typ.
[4]
Max.
Unit
V
V
V
V
µA
µA
I
CC
I
SB1
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V,
f = f
max
CE > V
CC
– 0.2V
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, Vcc=3.3V
I
SB2
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ.)
Max.
6
8
Unit
pF
pF
Thermal Resistance
Description
Thermal Resistance
(Junction to Ambient)
[5]
Thermal Resistance
(Junction to Case)
[5]
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Test Conditions
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board
Symbol
Θ
JA
Θ
JC
BGA
55
16
Units
°C/W
°C/W
3
WCMA2016U4X
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
Typ
10%
GND
Rise TIme: 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
V
TH
OUTPUT
Parameters
R1
R2
R
TH
V
TH
3.0V
1.105
1.550
0.645
1.75V
Unit
KOhms
KOhms
KOhms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[5]
t
R[6]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
CC
= 1.0V
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
0
70
Conditions
Min.
1.0
0.5
Typ.
[4]
Max.
3.6
7.5
Unit
V
µA
ns
ns
Data Retention Waveform
[7]
DATA RETENTION MODE
V
CC
CE or
V
CC(min)
t
CDR
V
DR
> 1.0 V
V
CC(min)
t
R
BHE.BLE
Note:
6. Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µs
or stable at V
CC(min.)
> 100
µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
4
WCMA2016U4X
Switching Characteristics
Over the Operating Range
[8]
70 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[10]
t
HZBE
WRITE CYCLE
[12]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BHE / BLE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[9, 11]
WE HIGH to Low Z
[9]
10
70
60
60
0
0
50
60
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[9]
OE HIGH to High Z
[9, 11]
CE LOW to Low Z
[9]
CE HIGH to High Z
[9, 11]
CE LOW to Power-Up
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
[9]
BHE / BLE HIGH to High Z
[9, 11]
5
25
0
70
70
10
25
5
25
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min
Max
Unit
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and
output loading of the specified I
OL
/I
OH
and 30 pF load capacitance.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less
than t
LZWE
for any given device.
10. If both byte enables are toggled together this value is 10ns
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured
when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the
edge of the signal that terminates the write..
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
