DATASHEET
CA5420A
0.5MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifiers
The CA5420A is an integrated circuit operational amplifier that
combines PMOS transistors and bipolar transistors on a single
monolithic chip. It is designed and guaranteed to operate in
microprocessor logic systems that use V+ = 5V, V- = GND, since it
can operate down to ±1V supplies. It will also be suitable for 3.3V
logic systems.
The CA5420A BiMOS operational amplifier features
gate-protected PMOS transistors in the input circuit to provide
very high input impedance, very low input currents (less than
1pA). The internal bootstrapping network features a unique
guardbanding technique for reducing the doubling of leakage
current for every +10°C increase in temperature. The CA5420A
operates at total supply voltages from 2V to 20V either single or
dual supply. This operational amplifier is internally phase
compensated to achieve stable operation in the unity gain
follower configuration. Additionally, it has access terminals for a
supplementary external capacitor if additional frequency roll-off is
desired. Terminals are also provided for use in applications
requiring input offset voltage nulling. The use of PMOS in the
input stage results in common-mode input voltage capability
down to 0.45V below the negative supply terminal, an important
attribute for single supply application. The output stage uses a
feedback OTA type amplifier that can swing essentially from
rail-to-rail. The output driving current of 1.0mA (Min) is provided by
using nonlinear current mirrors.
This device has guaranteed specifications for 5V operation
over the full military temperature range of -55°C to +125°C.
The CA5420A has the same 8 lead pinout used for the industry
standard 741.
FN1925
Rev 9.00
February 11, 2015
Features
• CA5420A at 5V supply voltage with full military temperature
range guaranteed specifications
• CA5420A guaranteed to operate from ±1V to ±10V supplies
• 2V supply at 350µA supply current
• 1pA (Typ) input current (essentially constant to +85°C)
• Rail-to-rail output swing (Drive ±2mA into 1kΩ load)
• Pin compatible with 741 op amp
• Pb-free (RoHS compliant)
Applications
• pH probe amplifiers
• Picoammeters
• Electrometer (High Z) instruments
• Portable equipment
• Inaccessible field equipment
• Battery dependent equipment (medical and military)
• 5V logic systems
• Microprocessor interface
X1
-
BiMOS
+
BiMOS
X1
BUFFER AMPS;
BOOTSTRAPPED
INPUT PROTECTION
NETWORK
HIGH GAIN
(50k)
TA BUFER
(X2)
FIGURE 1. FUNCTIONAL DIAGRAM
FN1925 Rev 9.00
February 11, 2015
Page 1 of 9
CA5420A
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
CA5420AMZ
NOTES:
1. Add “96” suffix for Tape and Reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for
CA5420A.
For more information on MSL please see techbrief
TB363.
PART
MARKING
5420 AMZ
TEMP. RANGE
(°C)
-55 to +125
PACKAGE
(RoHS Compliant)
8 Ld SOIC
PKG.
DWG. #
M8.15
Pin Configuration
CA5420A
(8 LD SOIC)
TOP VIEW
OFFSET
1
NULL
INV.
2
INPUT
NON-INV.
INPUT
V-
3
4
-
+
8
7
6
5
STROBE
V+
OUTPUT
OFFSET
NULL
Pin is connected to Case.
FN1925 Rev 9.00
February 11, 2015
Page 2 of 9
CA5420A
Absolute Maximun Ratings
Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . . . . . . . . 22V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V+ + 8V) to (V- -0.5V)
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note
4).
. . . . . . . . . . . . . . . . . . . . . Indefinite
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Thermal Information
Thermal Resistance (Typical,
Note 5)
JA
(°C/W)
JC
(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
157
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range (All Types) . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Short circuit may be applied to ground or to either supply.
5.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
Electrical Specifications
PARAMETER
Input Resistance
Input Capacitance
Output Resistance
Equivalent Input
Noise Voltage
Short-Circuit Current To Opposite Source
Supply
Sink
Gain Bandwidth Product
Slew Rate
Transient Response
Typical Values Intended Only for Design Guidance. V+ = +5V; V- = GND, T
A
= +25°C
SYMBOL
R
I
C
I
R
O
e
N
f = 1kHz
f = 10kHz
I
OM
+
I
OM
-
f
T
SR
R
S
= 100Ω
TEST CONDITIONS
CA5420A
150
4.9
300
62
38
2.6
2.4
0.5
0.5
R
L
= 2kΩ, C
L
= 100pF
0.7
15
20
2
A
V
= 1
A
V
= 1
2V
P-P
Input
2V
P-P
Input
8
4.5
UNITS
TΩ
pF
Ω
nV/Hz
nV/Hz
mA
mA
MHz
V/µs
µs
%
µA
mA
µs
µs
Rise Time
Overshoot
t
r
OS
I
8
+
I
8
-
0.01%
0.10%
Current from Terminal 8 To V-
Current from Terminal 8 To V+
Settling Time
+
Electrical Specifications
T
A
= +25
°
C, V+ = 5V, V- = 0, Unless Otherwise Specified.
CA5420A
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Common Mode Rejection Ratio
Common Mode Input Voltage Range
SYMBOL
V
IO
I
IO
I
I
CMRR
V
lCR
+
V
lCR
-
V
O
= 2.5V
V
O
= 2.5V
V
O
= 2.5V
TEST
CONDITIONS
MIN
(Note
6)
TYP
1
0.02
0.02
MAX
(Note
6)
5
4
5
UNITS
mV
pA
pA
dB
V
V
CM
= 0 to 3.7V, V
O
= 2.5V
V
O
= 2.5V
V+
= 1V;
V-
= 1V
R
L
=
R
L
= 10kΩ
R
L
= 2kΩ
75
3.7
83
4
-0.3
0
V
dB
dB
dB
dB
mA
Power Supply Rejection Ratio
Large Signal Voltage Gain
V
O
= 0.5 to 4V
V
O
= 0.5 to 4V
V
O
= 0.7 to 3V
Source Current
PSRR
A
OL
70
85
85
70
1.2
83
87
87
85
2.7
I
SOURCE
V
O
= 0V
FN1925 Rev 9.00
February 11, 2015
Page 3 of 9
CA5420A
Electrical Specifications
T
A
= +25
°
C, V+ = 5V, V- = 0, Unless Otherwise Specified. (Continued)
CA5420A
PARAMETER
Sink Current
Output Voltage
SYMBOL
I
SINK
V
OM
+
V
OM
-
V
OM
+
V
OM
-
V
OM
+
V
OM
-
R
L
= 2kΩ
R
L
= 10kΩ
V
O
= 5V
R
L
=
TEST
CONDITIONS
MIN
(Note
6)
1.2
4.85
TYP
2.1
4.94
0.13
MAX
(Note
6)
UNITS
mA
V
0.15
V
V
4.7
4.9
0.12
0.15
V
V
3.5
4.6
0.1
0.15
550
600
V
µA
µA
Supply Current
I
SUPPLY
V
O
= 0V
V
O
= 2.5V
400
430
Electrical Specifications
temperature range, -55°C to +125°C.
T
A
= -55
°
C to +125
°
C, V+ = 5V, V- = 0, Unless Otherwise Specified. Boldface limits apply across the operating
CA5420A
PARAMETER
Input Offset Voltage
Input Offset Current
Up to T
A
= +85°C
Input Current
Up to T
A
= +85°C
Common Mode Rejection Ratio
Common Mode Input Voltage Range
SYMBOL
V
IO
I
IO
I
I
TEST
CONDITIONS
V
O
= 2.5V
V
O
= 2.5V
MIN
(Note
6)
TYP
2
1.5
2
MAX
(Note
6)
10
3
10
5
15
UNITS
mV
nA
pA
nA
pA
dB
V
V
O
= 2.5V
2
10
CMRR
V
lCR
+
V
lCR
-
V
CM
= 0 to 3.7V,
V
O
= 2.5V
V
O
= 2.5V
V+
= 1V;
V-
= 1V
R
L
=
R
L
= 10kΩ
R
L
= 2kΩ
70
3.7
80
4
-0.3
0
V
dB
Power Supply Rejection Ratio
Large Signal Voltage Gain
V
O
= 0.5 to 4V
V
O
= 0.7 to 4V
V
O
= 0.7 to 2.5V
Source Current
Sink Current
Output Voltage
PSRR
A
OL
70
83
65
80
70
1
1
4.8
75
87
80
2.7
2.1
4.9
0.16
0.2
dB
dB
dB
mA
mA
V
V
V
0.2
V
V
0.2
600
650
V
µA
µA
I
SOURCE
I
SINK
V
OM
+
V
OM
-
V
OM
+
V
OM
-
V
OM
+
V
OM
-
V
O
= 0V
V
O
= 5V
R
L
=
R
L
= 10kΩ
4.7
4.9
0.15
R
L
= 2kΩ
3
4
0.14
Supply Current
I
SUPPLY
V
O
= 0V
V
O
= 2.5V
430
480
FN1925 Rev 9.00
February 11, 2015
Page 4 of 9
CA5420A
Electrical Specifications
For Equipment Design at V
SUPPLY
=
±
1V, T
A
= +25
°
C, Unless Otherwise Specified.
CA5420A
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Large Signal Voltage Gain
SYMBOL
V
IO
I
IO
I
I
A
OL
TEST
CONDITIONS
MIN
(Note
6)
TYP
2
0.01
0.02
MAX
(Note
6)
5
4
5
UNITS
mV
pA
pA
kV/V
dB
µV/V
dB
V
V
R
L
= 10kΩ
10
80
100
100
560
Common Mode Rejection Ratio
CMRR
50
65
0.5
-1.3
32
425
Common Mode Input Voltage Range
V
lCR
+
V
lCR
-
0.2
-1
Power Supply Rejection Ratio
PSRR
70
R
L
=
µV/V
dB
V
V
90
0.95
-0.91
350
0.7
4
650
1.1
Maximum Output Voltage
V
OM
+
V
OM
-
0.9
-0.85
Supply Current
Device Dissipation
Input Offset Voltage Temperature Drift
I
SUPPLY
P
D
V
IO
/T
µA
mW
µV/°C
Electrical Specifications
For Equipment Design at V
SUPPLY
=
±
10V, T
A
= +25
°
C, Unless Otherwise Specified.
CA5420A
TEST
CONDITIONS
MIN
(Note
6)
MAX
(Note
6)
5
4
5
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Large Signal Voltage Gain
Common Mode Rejection Ratio
Common Mode Input Voltage Range
Power Supply Rejection Ratio
Maximum Output Voltage
Supply Current
Device Dissipation
Input Offset Voltage
Temperature Drift
SYMBOL
V
IO
I
IO
I
I
A
OL
CMRR
TYP
2
0.03
0.05
UNITS
mV
pA
pA
kV/V
dB
R
L
= 10kΩ
20
80
70
100
100
100
80
9.3
-10.3
32
320
90
9.9
-9.85
450
9
4
1000
14
320
µV/V
dB
V
V
µV/V
dB
V
V
µA
mW
µV/°C
V
lCR
+
V
lCR
-
PSRR
9
-10
70
V
OM
+
V
OM
-
I
SUPPLY
P
D
V
IO
/T
R
L
=
9.7
-9.7
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN1925 Rev 9.00
February 11, 2015
Page 5 of 9
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