CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V
REF
+ = 2V, V
DD
= V
AA
+ = 5V, V
AA
- = V
REF
- = V
SS
= GND, f
CLK
= 25MHz
Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
SYSTEM PERFORMANCE
Resolution
Input Errors
Integral Linearity
Error
Differential Linearity
Error
Offset Error
(Unadjusted)
Gain Error
(Unadjusted)
CA3304A
CA3304
CA3304A
CA3304
CA3304A
CA3304
CA3304A
CA3304
4
-
-
-
-
-
-
-
-
-
±0.1
±0.125
±0.1
±0.125
-
-
-
-
-
±0.125
±0.25
±0.125
±0.25
±0.75
±1.0
±0.75
±1.0
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
DYNAMIC CHARACTERISTICS
(Input Signal Level 0.5dB Below Full Scale)
Conversion Timing
Aperture Delay
f
S
= 25MHz, f
IN
= 100kHz
f
S
= 25MHz, f
IN
= 5MHz
f
S
= 25MHz, f
IN
= 100kHz
f
S
= 25MHz, f
IN
= 5MHz
f
S
= 25MHz, f
IN
= 100kHz
f
S
= 25MHz, f
IN
= 5MHz
Effective Number of Bits, ENOB
f
S
= 25MHz, f
IN
= 100kHz
f
S
= 25MHz, f
IN
= 5MHz
ANALOG INPUTS
Input Range
Input Loading
Full Scale Input Range
Input Capacitance
Input Current
V
IN
= 2V (Note 2)
(Notes 1, 4)
0.5
-
-
-
10
150
V
AA
-
200
V
pF
µA
-
-
-
-
-
-
-
-
-
3
23.7
23.6
23.4
22.8
-34.5
-31.0
3.67
3.57
-
-
-
-
-
-
-
-
-
ns
dB
dB
dB
dB
dBc
dBc
Bits
Bits
Signal to Noise Ratio, SNR
RMS Signal
=
RMS Noise
Signal to Noise Ratio, SINAD
RMS Signal
=
RMS Noise + Distortion
Total Harmonic Distortion, THD
2
CA3304, CA3304A
Electrical Specifications
T
A
= 25
o
C, V
REF
+ = 2V, V
DD
= V
AA
+ = 5V, V
AA
- = V
REF
- = V
SS
= GND, f
CLK
= 25MHz
Unless Otherwise Specified
(Continued)
TEST CONDITIONS
(Note 4)
MIN
-
-
TYP
25
40
MAX
f
CLK
/2
-
UNITS
MHz
MHz
PARAMETER
Allowable Input Bandwidth
-3dB Input Bandwidth
REFERENCE INPUTS
Input Range
V
REF
+ Range
V
REF
- Range
Input Loading
DIGITAL INPUTS
Digital Input
Maximum V
IN
, Low
CLOCK
CE1, CE2
Minimum V
IN
, High
CLOCK
CE1, CE2
Input Leakage, Except CLK
Input Leakage, CLK
DIGITAL OUTPUTS
Digital Outputs
Output Low (Sink) Current
Output High (Source) Current
Three-State Leakage Current
TIMING CHARACTERISTICS
Conversion Timing
Maximum Conversion Speed
Auto-Balance Time (
φ
1)
Sample Time (
φ
2)
Output Timing
Data Valid Delay
Data Hold Time
Output Enable Time
Output Disable Time
POWER SUPPLY CHARACTERISTICS
Device Current, I
AA
Resistor Ladder Impedance
(Note 4)
(Note 4)
V
IN
= 5V, CLK = Low
V
AA
-
+0.5
V
AA
-
640
-
-
-
V
AA
+
V
AA
+ -
0.5
960
V
V
Ω
(Notes 3, 4)
(Note 4)
(Notes 3, 4)
(Note 4)
V = 0V, 5V
(Note 3)
-
-
0.7 x V
AA
0.7 x
V
DD
-
-
-
-
-
-
-
±100
0.3 x V
AA
0.3 x
V
DD
-
-
±1
±150
V
V
V
V
µA
µA
V
O
= 0.4V
V
O
= 4.6V
V
O
= 0V, 5V
6
-3
-
-
-
±0.2
-
-
±5
mA
mA
µA
CLK = Square Wave
25
20
20
35
-
-
30
25
15
10
-
MSPS
ns
ns
ns
ns
ns
ns
-
5000
40
-
-
-
(Note 4)
(Note 4)
-
15
-
-
Continuous Clock
Continuous
φ
2
Continuous
φ
1
-
-
-
-
-
-
5.5
0.4
2
1.5
5
5
-
-
-
-
10
20
mA
mA
mA
mA
mA
mA
Device Current, I
DD
V
AA
+ = 5V,
V
SS
= CE1 = V
AA
- = CLK = GND
V
AA
+ = 7V
NOTES:
Continuous Clock
Continuous
φ
2
Continuous
φ
1
1. Full scale input range, V
REF
+ - V
REF
-, may be in the range of 0.5V to V
AA
+ -V
AA
- volts. Linearity errors increase at lower full scale ranges,
however.
2. Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and VDD
voltage.
3. The CLK input is a CMOS inverter with a 50kΩ feedback resistor. It operates from the V
AA
+ and V
AA
- supplies. It may be AC-coupled
with a 1V
P-P
minimum source.
4. Parameter not tested, but guaranteed by design or characterization.
3
CA3304, CA3304A
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
Bit 1
Bit 2
Bit 3
Bit 4
DC
OF
CE2
V
SS
CE1
V
AA
+
V
IN
V
REF
+
V
REF
-
V
AA
-
CLK
V
DD
Bit 1 (LSB).
Bit 2.
Bit 3.
Bit 4 (MSB).
Data Change.
Overflow.
Three-State Output Enable Input, active low. See the Chip Enable Truth Table.
Digital Ground.
Three-State Output Enable Input, active high. See the Chip Enable Truth Table.
Analog Power Supply, +5V.
Analog Signal Input.
Reference Voltage Positive Input.
Reference Voltage Negative Input.
Analog Ground.
Clock Input.
Digital Power Supply, +5V.
CHIP ENABLE TRUTH TABLE
CE1
0
1
X
X = Don't Care
TABLE 1. OUTPUT CODE TABLE
INPUT VOLTAGE (V)
CODE
DESCRIPTION
Zero
1 LSB
2 LSB
•
•
•
•
1
/ Full Scale -1 LSB
2
1
/ Full Scale
2
1
/ Full Scale +1 LSB
2
DESCRIPTION
Output Data Bits
(High = True)
CE2
1
1
0
BIT 1 - BIT 4
Valid
Three-State
Three-State
DC, OF
Valid
Valid
Three-State
OUTPUT CODE
3.2V
0V
0
0.2
0.4
•
•
•
•
1.4
1.6
1.8
•
•
•
•
2.8
3.0
3.2
0.2
4.8V
0V
0
0.3
0.6
•
•
•
•
2.1
2.4
2.7
•
•
•
•
4.2
4.5
4.8
0.3
OF
0
0
0
•
•
•
•
0
0
0
•
•
•
•
0
0
1
B4
0
0
0
•
•
•
•
0
1
1
•
•
•
•
1
1
1
B3
0
0
0
•
•
•
•
1
0
0
•
•
•
•
1
1
1
B2
0
0
1
•
•
•
•
1
0
0
•
•
•
•
1
1
1
B1
0
1
0
•
•
•
•
1
0
1
•
•
•
•
0
1
1
DECIMAL
COUNT
0
1
2
•
•
•
•
7
8
9
•
•
•
•
14
15
31
V
REF
+ = 1V
V
REF
- = -1V
-1.000
-0.875
-0.750
•
•
•
•
-0.125
0
0.125
•
•
•
•
0.750
0.875
1.000
0.125
1.6V
0V
0
0.1
0.2
•
•
•
•
0.7
0.8
0.9
•
•
•
•
1.4
1.5
1.6
0.1
2V
0V
0
0.125
0.250
•
•
•
•
0.875
1.000
1.125
•
•
•
•
1.750
1.875
2.000
0.125
•
•
•
•
Full Scale -1 LSB
Full Scale
Overflow
Step Size
NOTE:
1. The voltages listed are the ideal centers of each output code shown as a function of its associated reference voltage See Ideal Transfer
Curve Figure 6. The output code should exist for an input equal to the ideal center voltage
±
1
/
2
of the step size.
4
CA3304, CA3304A
Functional Diagram
φ
2
V
AA
+
V
DD
16
OUTPUT
REGISTER
D Q
CLK
THREE-STATE
DRIVERS
5 DATA
CHANGE
φ
2
φ
1
V
IN
11
1
/ R
2
φ
1
φ
1
φ
1
10
D
COUNT
16
Q
D Q
CLK
6 OVERFLOW
12
V
REF
+
R
†
CAB #16
LATCH
16
D Q
CLK
COUNT
ENCODER
8
LOGIC
Q
D
ARRAY
LATCH
8
4 BIT 4
R
†
CAB #8
R
D Q
CLK
3 BIT 3
D Q
CLK
2 BIT 2
R
V
REF
-
1
13
50kΩ
CLOCK
15
/
2
R
D
COUNT
1
Q
†
CAB COMPARATOR #1
φ
1 (AUTO BALANCE)
φ
2 (SAMPLE UNKNOWN)
LATCH
0
14
V
AA
-
8
V
SS
D Q
CLK
1 BIT 1 (LSB)
9 CE1
7 CE2
†
Cascaded Auto Balance (CAB)
NOTE: CE1 and CE2 inputs and data outputs have standard CMOS protection networks to V
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
