Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for
details..
Electrical Specifications
PARAMETER
T
A
= 25
o
C, V+ = 5V, Zero Pot Centered, Gain Pot = 2.4kΩ, Unless Otherwise Specified
TEST CONDITIONS
MIN
4.5
100kΩ to V+ on Pins 3, 4, 5
-
-
Pins 10 and 11
V
11
-V
10
= 0V, Read Decoded Output
V
11
-V
10
= 900mV, Read Decoded Output
Notes 1 and 2
-
-12
846
-1
TYP
5
-
100
-80
-
-
-
MAX
5.5
17
-
-
+12
954
+1
UNITS
V
mA
MΩ
nA
mV
mV
Count
Operating Supply Voltage Range, V+
Supply Current, I+
Input Impedance, Z
I
Input Bias Current, I
IB
Unadjusted Zero Offset
Unadjusted Gain
Linearity
Conversion Rate
Slow Mode
Fast Mode
Conversion Control Voltage (Hold Mode)
at Pin 6
Common Mode Input Voltage Range, V
ICR
BCD Sink Current at Pins 1, 2, 15, 16
Digit Select Sink Current at Pins 3, 4, 5
Zero Temperature Coefficient
Gain Temperature Coefficient
NOTES:
Notes 3, 4
V
BCD
≥
0.5V, at Logic Zero State
V
DIGIT
Select = 4V at Logic Zero State
V
I
= 0V, Zero Pot Centered
V
I
= 900mV, Gain Pot = 2.4kΩ
Pin 6 = Open or GND
Pin 6 = 5V
-
-
0.8
4
96
1.2
-
-
1.6
Hz
Hz
V
-0.2
0.4
1.6
-
-
-
1.6
2.5
10
0.005
+0.2
-
-
-
-
V
mA
mA
µV/
o
V
%/
o
C
1. Apply 0V across V
11
to V
10
. Adjust zero potentiometer to give 000mV reading. Apply 900mV to input and adjust gain potentiometer to
give 900mV reading.
2. Linearity is measured as a difference from a straight line drawn through zero and positive full scale. Limits do not include
±0.5
count bit
digitizing error.
3. For applications where low input pin 10 is not operated at pin 7 potential, a return path of not more than 100kΩ resistance must be provided
for input bias currents.
4. The common mode input voltage above ground cannot exceed +0.2V if the full input signal range of 999mV is required at pin 11. That is,
pin 11 may not operate higher than 1.2V positive with respect to ground or 0.2V negative with respect to ground. If the maximum input
signal is less than 999mV, the common mode input voltage may be raised accordingly.
3
CA3162
Timing Diagram
12
5 (LSD)
PIN NUMBER
200mV
500mV
reference constant current source of opposite polarity is
connected. The number of clock counts that elapse before the
charge is restored to its original value is a direct measure of
the signal induced current. The restoration is sensed by the
comparator, which in turn latches the counter. The count is
then multiplexed to the BCD outputs.
The timing for the CA3162E is supplied by a 786Hz ring
oscillator, and the input at pin 6 determines the sampling rate.
A 5V input provides a high speed sampling rate (96Hz), and
grounding or floating pin 6 provides a low speed (4Hz) sam-
pling rate. When pin 6 is fixed at +1.2V (by placing a 12K
resistor between pin 6 and the +5V supply) a “hold” feature is
available. While the CA3162E is in the hold mode, sampling
continues at 4Hz but the display data are latched to the last
reading prior to the application of the 1.2V. Removal of the
1.2V restores continuous display changes. Note, however,
that the sampling rate remains at 4Hz.
Figure 1 shows the timing of sampling and digit select pulses
for the high speed mode. Note that the basic A/D conversion
process requires approximately 5ms in both modes.
The “EEE” or “---” displays indicate that the range of the system
has been exceeded in the positive or negative direction,
respectively. Negative voltages to -99mV are displayed with the
minus sign in the MSD. The BCD code is 1010 for a negative
overrange (---) and 1011 for a positive overrange (EEE).
4 (MSD)
500mV
3 (NSD)
500mV
2ms/DIV.
FIGURE 1. HIGH SPEED MODE
Detailed Description
The Functional Block Diagram of the CA3162E shows the V/I
converter and reference current generator, which is the heart
of the system. The V/I converter converts the input voltage
applied between pins 10 and 11 to a current that charges the
integrating capacitor on pin 12 for a predetermined time inter-
val. At the end of the charging interval, the V/I converter is dis-
connected from the integrating capacitor, and a band gap
NOTE 1
0.27µF
NOTE 2
+5V
0.1
µF
NORMAL
8
LOW SPEED MODE:
V6 = GROUND OR
OPEN
HOLD:
V
6
= 1.2V
6
9
12
14
16
MSD
NSD
COMMON
ANODE LED
DISPLAYS
LSD
POWER
2N2907, 2N3906
OR EQUIV.
a
5
3
4
a
b
f
g
c
e
d
c
e
b
f
a
b
g
c
d
f
g
e
d
13
CA3161E
12
11
10
9
15
14
8
3
HIGH SPEED MODE:
V
6
= 5V
CA3162E
DIGIT
DRIVERS
BCD
OUTPUTS
11
HIGH
INPUTS
LOW
10
13
GAIN
ADJ
10
kΩ
7
16
15
1
2
6
2
1
7
R1
150Ω
CA3162E
PINS
3, 4, 5
1kΩ
DIGIT
DRIVER
CA3162E
PINS
1, 2, 15, 16
75Ω
R2
150Ω
R3
150Ω
NOTES:
1. The capacitor used here must be a low dielectric absorption type
such as a polyester or polystyrene type.
2. This capacitor should be placed as close as possible to the power
and ground Pins of the CA3161E.
BCD SEGMENT
DRIVERS
FIGURE 2. BASIC DIGITAL READOUT SYSTEM USING THE CA3162E AND THE CA3161E
4
CA3162
CA3162E Liquid Crystal Display (LCD) Application
Figure 3 shows the CA3162E in a typical LCD application.
LCDs may be used in favor of LED displays in applications
requiring lower power dissipation, such as battery-operated
equipment, or when visibility in high-ambient-light conditions
is desired.
Multiplexing of LCD digits is not practical, since LCDs must
be driven by an AC signal and the average voltage across
each segment is zero. Three CD4056B liquid-crystal
decoder/drivers are therefore used. Each CD4056B contains
an input latch so that the BCD data for each digit may be
latched into the decoder using the inverted digit-select out-
puts of the CA3162E as strobes.
The capacitors on the outputs of inverters G3 and G4 filter
out the decode spikes on the MSD and NSD signals. The
capacitors and pull-up resistors connected to the MSD, NSD
and LSD outputs are there to shorten the digit drive signal
thereby providing proper timing for the CD4056B latches.
Inverters G1 and G2 are used as an astable multivibrator to
provide the AC drive to the LCD backplane. Inverters G3, G4
and G5 are the digit-select inverters and require pull-up
resistors to interface the open-collector outputs of the
CA3162E to CMOS logic. The BCD outputs of the CA3162E
may be connected directly to the corresponding CD4056B
inputs (using pull-up resistors). In this arrangement, the
CD4056B decodes the negative sign (-) as an “L” and the
positive overload indicator (E) as an “H”.
The circuit as shown in Figure 3 using G7, G8 and G9 will
decode the negative sign (-) as a negative sign (-), and the
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