Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW
Maximum Junction Temperature (Plastic Package) . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3102 is isolated from the substrate by an integral diode. The substrate (Terminal 9) must be connected
to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
T
A
= 25
o
C
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
Input Offset Voltage (Figures 1, 4)
Input Offset Current (Figure 1)
Input Bias Current (Figures 1, 5)
Temperature Coefficient
Magnitude of Input Offset Voltage
V
IO
I
IO
I
B
I
3
= I
9
= 2mA
-
-
-
-
0.25
0.3
13.5
1.1
5.0
3.0
33
-
mV
µA
µA
µV/
o
C
∆V
IO
----------------
∆T
DC CHARACTERISTICS FOR EACH TRANSISTOR
DC Forward Base-to-Emitter Voltage
(Figure 6)
VBE
∆V
BE
--------------
-
∆T
I
CBO
V
(BR)CEO
V
(BR)CBO
V
(BR)CIO
V
(BR)EBO
V
CE
= 6V, I
C
= 1mA
V
CE
= 6V, I
C
= 1mA
674
-
774
-0.9
874
-
mV
mV/
o
C
Temperature Coefficient of
Base-to-Emitter Voltage
(Figure 6)
Collector Cutoff Current (Figure 7)
Collector-to-Emitter Breakdown Voltage
Collector-to-Base Breakdown Voltage
Collector-to-Substrate Breakdown Voltage
Emitter-to-Base Breakdown Voltage
V
CB
= 10V, I
E
= 0
I
C
= 1mA, I
B
= 0
I
C
= 10µA, I
E
= 0
I
C
= 10µA, I
B
= I
E
= 0
I
E
= 10µA, I
C
= 0
-
15
20
20
5
0.0013
24
60
60
7
100
-
-
-
-
nA
V
V
V
V
DYNAMIC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
1/f Noise Figure (For Single Transistor)
(Figure 12)
Gain Bandwidth Product (For Single
Transistor) (Figure 11)
Collector-Base Capacitance (Figure 8)
NF
f
T
C
CB
f = 100kHz, R
S
= 500Ω,
I
C
= 1mA
V
CE
= 6V, I
C
= 5mA
I
C
= 0,
V
CB
= 5V
I
C
= 0, V
CI
= 5V
I
3
= I
9
= 2mA
Bias Voltage = -6V
Bias Voltage = -4.2V,
f = 10MHz
Note 3
Note 4
-
-
-
-
-
-
-
18
1.5
1.35
0.28
0.15
1.65
100
75
22
-
-
-
-
-
-
-
-
dB
GHz
pF
pF
pF
dB
dB
dB
Collector-Substrate
Capacitance (Figure 8)
Common Mode Rejection Ratio
AGC Range, One Stage (Figure 2)
Voltage Gain, Single-Ended Output
(Figures 2, 9, 10)
C
CI
CMRR
AGC
A
2
CA3102
Electrical Specifications
PARAMETER
Insertion Power Gain (Figure 3)
Noise Figure (Figure 3)
Input Admittance
T
A
= 25
o
C
(Continued)
SYMBOL
G
P
NF
Y
11
TEST CONDITIONS
V
CC
= 12V, for
Cascode
Configuration
I
3
= I
9
= 2mA. For
Diff. Amp.
Configuration
I
3
= I
9
= 4mA (Each
Collector I
C
≅
2mA)
f = 200MHz
Cascode
Cascode
Cascode (Figures
14, 16, 18)
Diff. Amp. (Figures
15, 17, 19)
Cascode
Diff. Amp.
Forward Transfer
Admittance
Y
21
Cascode (Figures
26, 28, 30)
Diff. Amp. (Figures
27, 29, 31)
Output Admittance
Y
22
Cascode (Figures
20, 22, 24)
Diff. Amp. (Figures
21, 23, 25)
NOTES:
3. Terminals 1 and 14 or 7 and 8.
4. Terminals 13 and 4 or 6 and 11.
MIN
-
-
-
-
-
-
-
-
-
-
TYP
23
4.6
1.5 + j2.45
0.878 + j1.3
0.0 - j0.008
0.0 - j0.013
17.9 - j30.7
-10.5 + j13
-0.503 - j15
0.071 + j0.62
MAX
-
-
-
-
-
-
-
-
-
-
UNITS
dB
dB
mS
mS
mS
mS
mS
mS
mS
mS
Reverse Transfer Admittance
Y
12
Schematic Diagram
CA3102E, CA3102M
1
14
13
4
12
8
7
6
11
Q
2
2
Q
3
Q
1
10
Q
6
Q
4
Q
5
3
5
SUBSTRATE
9
3
CA3102
Test Circuits
+6V
V+ (+6V)
1kΩ
V
OUT
+1V
1kΩ
V
O
S
1
-1V
BIAS
VOLTAGE
5
V
X
M
I
3
or I
9
12
1kΩ
10µF
S
2
M
S
1
(10)
2
Q
3
(Q
4
)
3 (9)
500Ω
V
IN
(8)
1
100Ω
(7) 14
S
2
1kΩ
M
Q
2
(Q
6
)
13 (6)
Q
1
(Q
5
)
100Ω
4
(11)
V- (-6V)
-6V
FIGURE 1. DC CHARACTERISTICS TEST CIRCUIT FOR CA3102
FIGURE 2. AGC RANGE AND VOLTAGE GAIN TEST CIRCUIT
FOR CA3102
1/2 CA3102
14(7)
Q
2
(Q
6
)
Q
1
(Q
5
)
0.005µF
5(12)
1(8)
SUBSTRATE
Q
3
(Q
4
)
2 (10)
5.6pF
3 (9)
4 (11)
13 (6)
2.7pF
5µF
100Ω
6V
2+
0.001
µF
5pF C
2
L
2
0.001µF
0.001µF
OUTPUT
R
L
= 50Ω
INPUT
R
G
= 50Ω
L
1
C
1
0.001µF
MA
2kΩ
1kΩ
FERRITE
BEADS
5kΩ
13kΩ
0.001µF
100pF
NOTES:
5. Numbers in parentheses refer to the other
half of the CA3102.
6. L
1
, L
2
- Approximately
1
/
2
Turn #18 Tinned
Copper Wire, 5/8” Diameter.
100pF
100pF
470pF
10kΩ
+12V
0.001µF
7. C
1
, C
2
- 15pF Variable Capacitors
(Hammarlund, MAC-15; or Equivalent).
FIGURE 3. 200MHz CASCODE POWER GAIN AND NOISE FIGURE TEST CIRCUIT
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