CEP04N7/CEB04N7
CEI04N7/CEF04N7
Electrical Characteristics
Parameter
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
b
Gate Threshold Voltage
Static Drain-Source
On-Resistance
Forward Transconductance
Dynamic Characteristics
c
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
b
c
Tc = 25 C unless otherwise noted
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(on)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
f
V
SD
V
GS
= 0V, I
S
= 2.5A
V
DS
= 480V, I
D
= 4A,
V
GS
= 10V
V
DD
= 300V, I
D
= 4A,
V
GS
= 10V, R
GEN
= 25Ω
Test Condition
V
GS
= 0V, I
D
= 250µA
V
DS
= 600V, V
GS
= 0V
V
GS
= 30V, V
DS
= 0V
V
GS
= -30V, V
DS
= 0V
V
GS
= V
DS
, I
D
= 250µA
V
GS
= 10V, I
D
= 2A
V
DS
= 40V, I
D
= 2A
2
2.7
1.3
505
95
55
21
34
88
28
37
5.7
20
2.5
1.6
40
65
160
60
48
Min
700
25
100
-100
4
3.5
Typ
Max
Units
V
µA
4
nA
nA
V
Ω
S
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
A
V
V
DS
= 25V, V
GS
= 0V,
f = 1.0 MHz
Drain-Source Diode Characteristics and Maximun Ratings
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature .
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% .
c.Guaranteed by design, not subject to production testing.
d.Limited only by maximum temperature allowed .
e .Pulse width limited by safe operating area .
f.Full package I
S(max)
= 2.5A .
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FPGA/CPLD
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