1.8 Volt Intel
®
Wireless Flash Memory
with 3 Volt I/O and SRAM (W30)
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary Datasheet
Product Features
Flash Performance
— 70 ns Initial Access Speed
— 25 ns Page-Mode Read Speed
— 20 ns Burst-Mode Read Speed
— Burst and Page Mode in All Blocks and
across All Partition Boundaries
— Enhanced Factory Programming:
3.5 µs per Word Program Time
— Programmable WAIT Signal Polarity
s
Flash Power
— V
CC
= 1.70 V – 1.90 V
— V
CCQ
= 2.20 V – 3.30 V
— Standby Current = 6 µA (typ.)
— Read Current = 7 mA
(4 word burst, typ.)
s
Flash Software
— 5/9 µs (typ.) Program/Erase Suspend Latency
Time
— Intel
®
Flash Data Integrator (FDI) and
Common Flash Interface (CFI) Compatible
s
Quality and Reliability
— Operating Temperature:
–25 °C to +85 °C
— 100K Minimum Erase Cycles
— 0.18 µm ETOX™ VII Process
s
Flash Architecture
— Multiple 4-Mbit Partitions
— Dual Operation: RWW or RWE
— Parameter Block Size = 4-Kword
— Main block size = 32-Kword
— Top and Bottom Parameter Devices
s
Flash Security
— 128-bit Protection Register: 64 Unique Device
Identifier Bits; 64 User OTP Protection
Register Bits
— Absolute Write Protection with V
PP
at Ground
— Program and Erase Lockout during Power
Transitions
— Individual and Instantaneous Block Locking/
Unlocking with Lock-Down
s
SRAM
— 70 ns Access Speed
— 16-bit Data Bus
— Low Voltage Data Retention
— S-V
CC
= 2.20 V – 3.30 V
s
Density and Packaging
— 32-Mbit Discrete in VF BGA Package
— 64-Mbit Discrete in µBGA* Package
— 56 Active Ball Matrix, 0.75 mm Ball-Pitch in
µBGA* and VF BGA Packages
— 32/4-, 64/8- and 128/TBD- Mbit (Flash +
SRAM) in a 80-Ball Stacked-CSP Package (14
mm x 8 mm)
— 16-bit Data Bus
s
The 1.8 Volt Intel
®
Wireless Flash Memory with 3 Volt I/O combines state-of-the-art Intel
®
Flash technology with
low power SRAM to provide the most versatile and compact memory solution for high performance, low power,
board constraint memory applications.
The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O offers a multi-partition, dual-operation flash
architecture that enables the device to read from one partition while programming or erasing in another partition.
This Read-While-Write or Read-While-Erase capability makes it possible to achieve higher data throughput rates
as compared to single partition devices and it allows two processors to interleave code execution because
program and erase operations can now occur as background processes.
The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O incorporates a new Enhanced Factory Programming
(EFP) mode to improve 12 V factory programming performance. This new feature helps eliminate manufacturing
bottlenecks associated with programming high density flash devices. Compare the EFP program time of 3.5 µs
per word to the standard factory program time of 8.0 µs per word and save significant factory programming time
for improved factory efficiency.
Additionally, the 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O includes block lock-down, programmable
WAIT signal polarity and is supported by an array of software tools. All these features make this product a perfect
solution for any demanding memory application.
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
290702-002
March 2001
Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 1.8 Volt Intel
®
Wireless Flash Memory (with 3 Volt I/O and SRAM) may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2000 - 2001.
*Other names and brands may be claimed as the property of others.
Preliminary
28F320W30, 28F3204W30, 28F6408W30, 28F640W30
Contents
1.0
Product Introduction
.................................................................................................1
1.1
1.2
Document Purpose................................................................................................ 1
Nomenclature ........................................................................................................1
Product Overview .................................................................................................. 2
Package Diagram.................................................................................................. 3
Package Dimensions............................................................................................. 4
Signal Descriptions................................................................................................ 5
Block Diagram ....................................................................................................... 6
Flash Memory Map................................................................................................ 6
Bus Operations...................................................................................................... 9
Flash Command Definitions .................................................................................. 9
Read Array ..........................................................................................................12
4.1.1 Asynchronous Mode...............................................................................12
4.1.2 Synchronous Mode ................................................................................12
Set Configuration Register (CR)..........................................................................13
4.2.1 Read Mode (RM)....................................................................................14
4.2.2 First Latency Count (LC2–0) ..................................................................14
4.2.3 WAIT Signal Polarity (WT) .....................................................................16
4.2.4 WAIT Signal Function.............................................................................17
4.2.5 Data Output Configuration (DOC) ..........................................................17
4.2.6 WAIT Configuration (WC).......................................................................18
4.2.7 Burst Sequence (BS)..............................................................................19
4.2.8 Clock Configuration (CC) .......................................................................20
4.2.9 Burst Wrap (BW) ....................................................................................21
4.2.10 Burst Length (BL2–0) .............................................................................21
Read Query Register...........................................................................................21
Read ID Register.................................................................................................21
Read Status Register ..........................................................................................22
4.5.1 Clear Status Register .............................................................................24
Read-While-Write/Erase......................................................................................24
Factory Program Mode........................................................................................24
Programming Voltage Protection (VPP)..............................................................25
Enhanced Factory Programming (EFP) ..............................................................25
5.3.1 EFP Requirements and Considerations .................................................26
5.3.2 Setup Phase...........................................................................................26
5.3.3 Program Phase ......................................................................................26
5.3.4 Verify Phase ...........................................................................................27
5.3.5 Exit Phase ..............................................................................................27
Write Protection (V
PP
< V
PPLK
) ...........................................................................27
2.0
Product Description
.................................................................................................. 2
2.1
2.2
2.3
2.4
2.5
2.6
3.0
Product Operations
................................................................................................... 9
3.1
3.2
4.0
Flash Read Modes
...................................................................................................12
4.1
4.2
4.3
4.4
4.5
4.6
5.0
Program and Erase Voltages
...............................................................................24
5.1
5.2
5.3
5.4
Preliminary
iii
28F320W30, 28F3204W30, 28F6408W30, 28F640W30
6.0
Flash Erase Mode
.................................................................................................... 27
6.1
6.2
Block Erase ......................................................................................................... 27
Erase Protection (V
PP
< V
PPLK
) .......................................................................... 28
Program/Erase Suspend..................................................................................... 28
Program/Erase Resume...................................................................................... 28
Block Lock........................................................................................................... 29
Block Unlock ....................................................................................................... 30
Lock-Down Block ................................................................................................ 30
Block Lock Operations during Erase Suspend.................................................... 30
WP# Lock-Down Control..................................................................................... 30
Protection Register Read .................................................................................... 32
Program Protection Register ............................................................................... 32
Protection Register Lock ..................................................................................... 33
Power-Up/Down Characteristics ......................................................................... 34
Power Supply Decoupling ................................................................................... 34
Flash Reset Characteristics ................................................................................ 34
Absolute Maximum Ratings ................................................................................ 35
Extended Temperature Operation....................................................................... 35
DC Characteristics .............................................................................................. 36
Discrete Capacitance (32-Mbit VF BGA Package) ............................................. 38
Stacked Capacitance (32/4 and 64/8 Stacked-CSP Package) ........................... 39
Flash Read Operations ....................................................................................... 40
Flash Write Operations ....................................................................................... 49
Flash Program and Erase Operations................................................................. 51
Reset Operations ................................................................................................ 51
SRAM Read Operation ....................................................................................... 53
SRAM Write Operation........................................................................................ 55
SRAM Data Retention Operation ........................................................................ 56
7.0
Flash Suspend/Resume Modes
.......................................................................... 28
7.1
7.2
8.0
Flash Security Modes
............................................................................................. 29
8.1
8.2
8.3
8.4
8.5
9.0
Flash Protection Register
..................................................................................... 32
9.1
9.2
9.3
10.0
Power and Reset Considerations
...................................................................... 34
10.1
10.2
10.3
11.0
Electrical Specifications
........................................................................................ 35
11.1
11.2
11.3
11.4
11.5
12.0
Flash AC Characteristics
...................................................................................... 40
12.1
12.2
12.3
12.4
13.0
SRAM AC Characteristics
..................................................................................... 53
13.1
13.2
13.3
14.0
Ordering Information
.............................................................................................. 58
Flash Write State Machine (WSM)
................................................................ 59
Flowcharts
............................................................................................................. 61
Common Flash Interface
................................................................................. 68
Appendix A
Appendix B
Appendix C
iv
Preliminary
28F320W30, 28F3204W30, 28F6408W30, 28F640W30
Revision History
Date of
Revision
09/19/00
03/14/01
Version
-001
-002
Original Version
28F3208W30 product references removed (product was discontinued)
28F640W30 product added
Revised Table 2,
Signal Descriptions (DQ
15–0
, ADV#, WAIT, S-UB#, S-LB#, V
CCQ
)
Revised Section 3.1,
Bus Operations
Revised Table 5,
Command Bus Definitions,
Notes 1 and 2
Revised Section 4.2.2,
First Latency Count (LC
2–0
);
revised Figure 6,
Data Output
with LC Setting at Code 3;
added Figure 7,
First Access Latency Configuration
Revised Section 4.2.3,
WAIT Signal Polarity (WT)
Added Section 4.2.4,
WAIT Signal Function
Revised Section 4.2.5,
Data Output Configuration (DOC)
Added Figure 8,
Data Output Configuration with WAIT Signal Delay
Revised Table 13,
Status Register DWS and PWS Description
Revised entire Section 5.0,
Program and Erase Voltages
Revised entire Section 5.3,
Enhanced Factory Programming (EFP)
Revised entire Section 8.0,
Flash Security Modes
Revised entire Section 9.0,
Flash Protection Register;
added Table 15,
Simulta-
neous Operations Allowed with the Protection Register
Revised Section 10.1,
Power-Up/Down Characteristics
Revised Section 11.3,
DC Characteristics. Changed
I
CCS,
I
CCWS,
I
CCES
Specs from
18 µA to 21µA; changed I
CCR
Spec from 12 mA to 15 mA (burst length = 4)
Added Figure 20,
WAIT Signal in Synchronous Non-Read Array Operation Wave-
form
Added Figure 21,
WAIT Signal in Asynchronous Page-Mode Read Operation
Waveform
Added Figure 22,
WAIT Signal in Asynchronous Single-Word Read Operation
Waveform
Revised Figure 23,
Write Waveform
Revised Section 12.4,
Reset Operations
Clarified Section 13.2,
SRAM Write Operation,
Note 2
Revised Section 14.0,
Ordering Information
Minor text edits
Description
Preliminary
v
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