Low Skew, 1-to-5
Differential-to-2.5V/3.3V LVPECL Fanout Buffer
G
ENERAL
D
ESCRIPTION
The 85314I-01 is a low skew, high performance 1-to-
5 Differential-to-2.5V/3.3V LVPECL Fanout Buffer.The
85314I-01 has two selectable clock inputs. The CLK0,
nCLK0 pair can accept most standarddifferential input
levels. The single-ended CLK1 can accept LVCMOS or
LVTTL input levels. The clock enable is inter nally
synchronized to eliminate runt clock pulses on the outputs during
asynchronous assertion/deassertion of the clockenable pin.
Guaranteed output and par t-to-par t skew character-
istics make the 85314I-01 ideal for those applications
demanding well defined performance and repeatability.
85314I-01
DATASHEET
F
EATURES
•
5 differential 2.5V/3.3V LVPECL outputs
•
Selectable differential CLK0, nCLK0 or LVCMOS inputs
•
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
CLK1 can accept the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 700MHz
•
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
•
Output skew: 30ps (maximum), TSSOP package
50ps (maximum), SOIC package
•
Part-to-part skew: 350ps (maximum)
•
Propagation delay: 1.8ns (maximum)
•
RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.05ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free RoHS-compliant package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
nCLK_EN
V
CC
nc
CLK1
CLK0
nCLK0
nc
CLK_SEL
V
EE
85314I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
85314I-01
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
85314I-01 REVISION G DECEMBER 19, 2014
1
©2014 Integrated Device Technology, Inc.
85314I-01 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 6
7, 8
9, 10
11
12
13, 17
14
15
16
18, 20
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
EE
CLK_SEL
nc
nCLK0
CLK0
CLK1
V
CC
Type
Output
Output
Output
Output
Output
Power
Input
Unused
Input
Input
Input
Power
Pullup
Pulldown
Pulldown
Pulldown
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
No connect.
Inverting differential clock input.
Non-inverting differential clock input.
Clock input. LVTTL / LVCMOS interface levels.
Positive supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock input.
19
nCLK_EN
Input
Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high. LVT-
TL / LVCMOS interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
Low Skew, 1-to-5
Differential-to-2.5V/3.3V LVPE
CL Fanout Buf
fer
2
REVISION G 12/19/14
85314I-01 DATA SHEET
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
nCLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK0, nCLK0
CLK1
CLK0, nCLK0
CLK1
Q0:Q4
Enabled
Enabled
Disabled; LOW
Disabled; LOW
Outputs
nQ0:nQ4
Enabled
Enabled
Disabled; HIGH
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs
as described in Table 3B.
F
IGURE
1. nCLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK0 or CLK1
0
1
nCLK0
1
0
Q0:Q4
LOW
HIGH
Outputs
nQ0:nQ4
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Polarity
Non Inverting
Non Inverting
REVISION G 12/19/14
3
Low Skew, 1-to-5
Differential-to-2.5V/3.3V LVPE
CL Fanout Buf
fer
85314I-01 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
20 Lead TSSOP
73.2°C/W (0 lfpm)
20 Lead SOIC
46.2°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
80
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
nCLK_EN, CLK_SEL
CLK1
nCLK_EN, CLK_SEL
CLK1
CLK1,
CLK_SEL, nCLK_EN
CLK1,
CLK_SEL, nCLK_EN
V
IN
= V
CC
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
-5
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
1.3
150
Units
V
V
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nCLK0
CLK0
nCLK0
CLK0
Test Conditions
V
CC
= V
IN
= 3.8V
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
V
CC
= 3.8V, V
IN
= 0V
-150
-5
0.15
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
0.5
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
Low Skew, 1-to-5
Differential-to-2.5V/3.3V LVPE
CL Fanout Buf
fer
4
REVISION G 12/19/14
85314I-01 DATA SHEET
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tjit (Ø)
tp
LH
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
CLK0, nCLK0
CLK1
Integration Range:
(12kHz - 20MHz)
1.0
0.05
1.4
1.8
30
50
350
20% to 80%
CLK0, nCLK0
CLK1
ƒ
≤
700MHz
ƒ
≤
250MHz
200
45
45
700
55
55
Test Conditions
Minimum
Typical
Maximum
700
300
Units
MHz
MHz
ps
ns
ps
ps
ps
ps
%
%
RMS Phase Jitter (Random); NOTE 5
Propagation Delay, Low to High; NOTE 1
Output Skew;
NOTE 3, 6
TSSOP Package
SOIC Package
Part-to-Part Skew; NOTE 4, 6
Output Rise/Fall Time
Output Duty Cycle
All parameters measured at f
MAX
unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Measured from V
CC
/2 input crossing point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: Please refer to the Phase Noise Plot.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
REVISION G 12/19/14
5
Low Skew, 1-to-5
Differential-to-2.5V/3.3V LVPE
CL Fanout Buf
fer
Microchip MCU
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