SU5321635D8F6CU
August 18, 2004
Ordering Information
Part Numbers
SM5321635D8F6CG
SB5321635D8F6CG
Description
16Mx32 (64MB), DDR, 100-pin DIMM, Unbuffered, Non-ECC,
16Mx16 Based, DDR266A, 25.40mm, 22
Ω
DQ termination.
16Mx32 (64MB), DDR, 100-pin DIMM, Unbuffered, Non-ECC,
16Mx16 Based, DDR266A, 25.40mm, 22
Ω
DQ termination,
Lead-Free Module.
16Mx32 (64MB), DDR, 100-pin DIMM, Unbuffered, Non-ECC,
16Mx16 Based, DDR266A, 25.40mm, 22
Ω
DQ termination,
Mixed Process Module.
16Mx32 (64MB), DDR, 100-pin DIMM, Unbuffered, Non-ECC,
16Mx16 Based, DDR266A, 25.40mm, 22
Ω
DQ termination,
Green Module.
16Mx32 (64MB), DDR, 100-pin DIMM, Unbuffered, Non-ECC,
16Mx16 Based, DDR266B, 25.40mm, 22
Ω
DQ termination.
16Mx32 (64MB), DDR, 100-pin DIMM, Unbuffered, Non-ECC,
16Mx16 Based, DDR266B, 25.40mm, 22
Ω
DQ termination,
Lead-Free Module.
16Mx32 (64MB), DDR, 100-pin DIMM, Unbuffered, Non-ECC,
16Mx16 Based, DDR266B, 25.40mm, 22
Ω
DQ termination,
Mixed Process Module.
16Mx32 (64MB), DDR, 100-pin DIMM, Unbuffered, Non-ECC,
16Mx16 Based, DDR266B, 25.40mm, 22
Ω
DQ termination,
Green Module.
Module Speed
PC2100 @ CL 2.0, 2.5
PC2100 @ CL 2.0, 2.5
SX5321635D8F6CG
PC2100 @ CL 2.0, 2.5
SG5321635D8F6CG
PC2100 @ CL 2.0, 2.5
SM5321635D8F6CH
SB5321635D8F6CH
PC2100 @ CL 2.5
PC2100 @ CL 2.5
SX5321635D8F6CH
PC2100 @ CL 2.5
SG5321635D8F6CH
PC2100 @ CL 2.5
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 0RH, United Kingdom, • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SU5321635D8F6CU
August 18, 2004
Revision History
• August 18, 2004
Changed the datasheet part number from SM5321635D8F6CU to SU5321635D8F6CU because of the addition
of new Module Process Technologies.
Added SB5321635D8F6CG, SX5321635D8F6CG, SG5321635D8F6CG, SB5321635D8F6CH,
SX5321635D8F6CH & SG5321635D8F6CH to the datasheet to represent the new Module Process Technolo-
gies.
• July 26, 2004
Updated the datasheet with the new Smart Modular logo.
• October 17, 2003
Changed byte 9 from 7.0ns to 7.5ns for DDR266A on page 8.
Changed V
DDSPD
max from 2.7 to 5.5 on page 14.
• April 8, 2003
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 0RH, United Kingdom, • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SU5321635D8F6CU
August 18, 2004
64MByte (16Mx32) DDR SDRAM Module - 16Mx16 based
100-pin DIMM, Unbuffered, Non-ECC
Features
•
•
•
•
•
•
•
Standard
:
Configuration
:
Cycle Time
:
CAS# Latency
:
Burst Length
:
Burst Type
:
No. of Internal
Banks per SDRAM :
JEDEC
Non-ECC
7.5ns
2.0, 2.5
2, 4, 8
Sequential/Interleave
4
•
•
•
•
•
•
•
Operating Voltage :
2.5V
Refresh
:
8K/64ms
Device Physicals :
400mil TSOP
Lead Finish
:
Gold
Length x Height
:
90.17mm x 25.40mm
No. of sides
:
Single-sided
Mating Connector (Examples)
Vertical
:
AMP-390213-1
100-pin DDR DIMM Pin List
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DQ0
V
SS
DQ1
DQS0
V
DD
DQ2
DQ3
V
DD
DQ8
DQ9
V
SS
DQS1
DQ10
V
DD
DQ11
V
SS
CK0
CK0#
V
DD
CKE1 (NC)
Pin Pin
No. Name
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A12
NC
A9
A7
V
SS
A5
A3
A1
A10
V
DD
BA0
WE#
CS0#
DQ16
V
SS
DQ17
DQS2
V
DD
DQ18
DQ19
Pin Pin
No. Name
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
V
DD
DQ24
DQ25
V
SS
DQS3
DQ26
V
SS
DQ27
SA0
V
REF
DQ4
V
SS
DQ5
DM0
V
DD
DQ6
DQ7
V
DD
DQ12
DQ13
Pin Pin
No. Name
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
V
SS
DM1
DQ14
V
DD
DQ15
V
SS
CK1
CK1#
V
DD
CKE0
A11
A8
A6
A4
V
SS
A2
A0
BA1
RAS#
V
DD
Pin Pin
No. Name
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
CAS#
CS1 (NC)
A13 (NC)
DQ20
V
SS
DQ21
DM2
V
DD
DQ22
DQ23
V
DD
DQ28
DQ29
V
SS
DM3
DQ30
V
SS
DQ31
SDA
100 SCL
( All specifications of this device are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 0RH, United Kingdom, • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SU5321635D8F6CU
August 18, 2004
Pin Description Table
Symbol
CK0, CK0#
CK1, CK1#
Type
SSTL,
Input
Polarity
Crossing Point
Function
The system clock inputs. All address and command lines are sampled on the cross
point of the rising edge of CK and falling edge of CK#. A Delay Locked Loop (DLL) cir-
cuit is driven from the clock inputs and output timing for read operations is synchronized
to the input clock.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated DDR SDRAM command decoder when low and disables
decoder when high. When decoder is disabled, new commands are ignored but previ-
ous operations continue. Physical Bank 0 is selected by CS0#.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define
the operations to be executed by the SDRAM.
Selects which of the four internal SDRAM banks is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8)
when sampled at the rising clock edge. In addition to the column address, A10/AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If
A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be pre-
charged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to
control which bank(s) to precharge. If AP is high, all banks will be precharged regard-
less of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank
to precharge.
Data and Input/Output pins.
Tha data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect.
Tha data strobes, associated with one data byte, sourced with data tranfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window. In
Read mode, the data strobe is sourced by the DDR SDRAMs and is sent at the leading
edge of the data window.
Address Pin used to select the Serial Presence Detect.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected on the system board from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected on the system board from the SCL bus line to V
DD
to act as a pullup.
Power and ground for the DDR SDRAM input buffers and core logic.
Reference voltage for SSTL2 inputs.
No Connection.
CKE0
SSTL,
Input
SSTL,
Input
SSTL,
Input
SSTL,
Input
SSTL,
Input
Active High
CS0#
Active Low
RAS#, CAS#,
WE#
BA0, BA1
A0~A9,
A10/AP,
A11~A12
Active Low
-
-
DQ0~DQ31
DM0~DM3
SSTL,
In/Out
SSTL,
Input
SSTL
In/Out
-
Active High
DQS0~DQS3
Negative &
Positive Edge
SA0
SDA
SCL
V
DD,
V
SS
V
REF
NC
LVTTL,
Input
LVTTL,
In/Out
LVTTL,
Input
Supply
Supply
-
-
-
-
-
-
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 0RH, United Kingdom, • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SU5321635D8F6CU
August 18, 2004
Block Diagram
CS0#
CKE0
S# CKE
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U1
UDQS
UDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
S# CKE
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U2
UDQS
UDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SCL
SA0
SPD
EEPROM
SCL SDA
SA0
SA1 SPD1
SA2
WP
SDA
A0~A12
BA0, BA1
RAS#
CAS#
WE#
CS0#
CKE0#
to all SDRAMs (U1~U2)
to all SDRAMs (U1~U2)
to all SDRAMs (U1~U2)
to all SDRAMs (U1~U2)
to all SDRAMs (U1~U2)
to all SDRAMs (U1~U2)
to all SDRAMs (U1~U2)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 0RH, United Kingdom, • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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