NOT RECOMMENDED FOR NEW DESIGNS
Micrel, Inc.
÷
2/4,
÷
4/5/6 CLOCK
GENERATION CHIP
Precision Edge
®
SY100S839V
Precision Edge
®
SY100S839V
FEATURES
s
s
s
s
s
3.3V and 5V power supply option
50ps output-to-output skew
50% duty cycle outputs
Synchronous enable/disable
Master Reset for synchronization
Precision Edge
®
DESCRIPTION
The SY100S839V is a low skew
÷2/4, ÷4/5/6
clock
generation chip designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The device can be driven
by either a differential or single-ended ECL/LVECL or, if
positive power supplies are used, PECL/LVPECL input
signal. In addition, by using the V
BB
output, a sinusoidal
source can be AC-coupled into the device. If a single-
ended input is to be used, the V
BB
output should be
connected to the /CLK input and bypassed to ground via
a 0.01µF capacitor. The V
BB
output is designed to act as
the switching reference for the input of the S839V under
single-ended input conditions. As a result, this pin can
only source/sink up to 0.5mA of current.
The common enable (/EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a
random state; the master reset (MR) input must be
asserted to ensure synchronization. For systems which
only use one S839V, the MR pin need not be exercised
as the internal divider designs ensures synchronization
between the
÷2/4,
and the
÷4/5/6
outputs of a single
device.
s
Internal 75K
Ω
input pull-down resistors
s
Available in 20-pin SOIC package
Precision Edge is a registered trademark of Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
Rev.: B
Amendment: /0
1
Issue Date: March 2006
Micrel, Inc.
Precision Edge
®
SY100S839V
AC ELECTRICAL CHARACTERISTICS
(1)
V
EE
= V
EE
(min) to V
EE
(max); V
CC
= GND
T
A
= –40
°
C
Symbol
f
MAX
t
PD
Parameter
Maximum Toggle Frequency
Propagation Delay to Output
CLK
➝
Output (Diff.)
CLK
➝
Output (S.E.)
MR
➝
Output
Within-Device Skew
(2)
Q
0
— Q
3
Part-to-Part
t
S
t
H
V
PP
V
CMR
Set-up Time
Hold Time
Q
0
— Q
3
(Diff.)
/EN
➝
/CLK
DIVSEL
➝
CLK
/CLK
➝
/EN
CLK
➝
DIVSEL
CLK
1000
725
675
600
—
—
250
400
100
150
250
-1.6
—
CLK
MR
Q
500
700
280
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
925
975
900
50
200
—
—
—
—
—
-0.4
100
—
—
550
T
A
= 0
°
C
1000
725
675
600
—
—
250
400
100
150
250
-1.7
—
500
700
280
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
925
975
900
50
200
—
—
—
—
—
-0.4
100
—
—
550
T
A
= +25
°
C
1000
725
675
610
—
—
250
400
100
150
250
-1.7
—
500
700
280
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
925
975
910
50
200
—
—
—
—
—
-0.4
100
—
—
550
T
A
= +85
°
C
Unit
MHz
ps
725
675
630
—
—
250
400
100
150
250
-1.7
—
500
700
280
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
925
975
930
50
200
—
—
—
—
—
-0.4
100
—
—
550
ps
ps
mV
V
ps
ps
ps
ps
1000
—
—
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
t
skew
Minimum Input Swing
(3)
Common Mode Range
(4), (5)
Reset Recovery Time
Minimum Pulse Width
Output Rise/Fall Times
(20% —80%)
t
RR
t
PW
tr
t
f
Notes:
1. Parametric values specified at:
-3.0V to -3.8V or -4.2V to -5.5V.
2. Skew is measured between outputs under identical transitions.
3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between V
PP
min. and 1V. The lower end of the CMR range varies 1:1 with V
EE
. The numbers in the spec table
assume a nominal V
EE
= –3.3V. Note for PECL operation, the V
CMR
(min) will be fixed at 3.3V – IV
CMR
(min)I.
5. Duty Cycle: (Min. 48%; Max. 52%) } over temp.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
4
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