NIS6201
Floating, Regulated Charge
Pump
The NIS6201 charge pump is designed to provide economical, low
level power to circuits above ground level potential, such as the drive
for ORing diodes. It is a very cost−effective replacement for a small,
isolated, switching power supply.
It contains an internal linear regulator, and a versatile charge pump
to allow bias voltage supplies to be transferred from a ground
referenced source to a higher potential. The design of the charge
pump allows for any isolation voltage required, as the high voltage
components are external to the pump and can be sized accordingly.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8 NB
CASE 751
1
6201
AYWW
G
•
•
•
•
•
Integrated Linear Regulator and Charge Pump
Thermal Limit Protection
Adjustable Voltage Output
High Voltage Isolation
This is a Pb−Free Device
6201
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Applications
•
ORing Diodes
•
Floating Supervisory Circuits
•
LED Driver
V
CC
PIN CONNECTIONS
N/C 1
N/C 2
SIGGND 3
COMP
4
(Top View)
8
7
6
5
PWRGND
DRIVE
V
REG
V
CC
0.50 V
Regulator
15 V
+
-
ORDERING INFORMATION
Device
NIS6201DR2G
Package
SOIC−8
(Pb−Free)
Shipping
†
3000 / Tape & Reel
+
-
150 mV
Overcharge
DRIVE
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1.0 MHz
Oscillator
SIGGND
COMP
V
REG
PWRGND
Figure 1. Charge Pump Block Diagram
©
Semiconductor Components Industries, LLC, 2011
January, 2011
−
Rev. 3
1
Publication Order Number:
NIS6201/D
NIS6201
PIN FUNCTION DESCRIPTION
Pin
1, 2
3
4
5
6
7
8
Symbol
N/C
SIGGND
COMP
V
CC
V
REG
DRIVE
PWRGND
No connection.
Ground reference pin for control circuits. This should be connected to power ground on the PCB.
The feedback and compensation network of the linear regulator are connected to this pin.
Input power to chip. There is an internal clamp at 15 V to allow for a shunt regulator circuit on this pin for
high voltage inputs.
This is the regulated output of the internal linear regulator.
Output drive of oscillator, that drives external diode/capacitor network.
Ground reference pin for driver current.
Description
MAXIMUM RATINGS
Rating
Input Voltage, Operating (Note 1)
Comp pin Voltage
Drive Current, Peak
Drive Current, Average
Thermal Resistance, Junction−to−Air
Min copper area
1 in
2
copper (1 oz, single sided)
Thermal Resistance, Junction−to−Lead (Pin 1)
Power Dissipation @ T
A
= 25°C
Min copper area
1 in
2
copper (1 oz, single sided)
Operating Temperature Range
Non−operating Temperature Range
Lead Temperature, Soldering (10 Sec)
Symbol
V
CC
V
comp
I
Dpk
I
Davg
Q
JA
Value
−0.3
to 15
4.5
3.0
0.05
175
114
41
.57
.88
−40
to 125
−55
to 150
260
°C
°C
°C
Unit
V
V
A
A
°C/W
Q
JL
P
max
°C/W
W
T
J
T
J
T
L
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Above this voltage, a series resistor is necessary to limit current into the shunt regulator.
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: V
CC
= 15 V, V
reg
= 12 V, DRIVE Pin open, T
J
= 25°C.)
Characteristic
OSCILLATOR
Frequency
DRIVER
On Resistance, High Side FET
On Resistance, Low Side FET
LINEAR REGULATOR
Reference Voltage, Pin 4
T
J
=
−40
to 125°C
Headroom (V
CC
–V
reg
) V
CC
= 7 V, I
drive
= 10 mA
TOTAL DEVICE
Minimum Operational Input Voltage
Bias Current (Operational)
Bias Current (COMP Pin = 600 mV)
V
CC
Zener Breakdown Voltage
V
min
I
Bias
I
Bias_SD
V
Zener
7.0
−
−
14.5
−
3.6
3.0
15
−
4.6
3.6
−
V
mA
mA
V
V
ref
V
head
490
475
−
500
505
155
510
525
220
mV
mV
R
DSon(hi)
R
DSon(low)
−
−
9.5
9.5
−
12
W
W
f
osc
0.9
1.3
1.45
MHz
Symbol
Min
Typ
Max
Unit
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2
NIS6201
BAS16LT1
1.0
mF
BAS16LT1
0.1
mF
7
6
22 k
0.1
mF
1.0 k
BAS16LT1
Load
NIS6111
5
12 V
8
NIS6201
3
4
Figure 2. Application Circuit with Better ORing Diode
1.0
mF
V
CC
48 V
+
PWR
GND
SIG
GND
COMP
Charge
Pump
0.1
mF
DRIVE
DC−DC
Converter
V
REG
1.0
mF
Figure 3. Application Circuit for Improved
Regulation and Transient Response
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3
NIS6201
V
CC
8.0 V
+
PWR
GND
SIG
GND
COMP
Charge
Pump
0.1
mF
DRIVE
1.0
mF
V
REG
1.0
mF
Figure 4. Current Regulated, Voltage Doubler
8.0 to 18 Vdc
220
5
V
CC
PWR GND
NIS6201
SIG GND
COMP
Drive 7
VREG
8
0.1
mF
3
4
6
13.7k
0.1
mF
1k
0.1
mF
0.1
mF
100
mA
to 2 mA
−12.5
V
1
mF
1
mF
Diodes are:
BAS16LT1 75V
or M1MA174T1 100V
Figure 5. Regulated, Negative Doubler Circuit
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4
NIS6201
OPERATING DESCRIPTION
DC Input
The Vcc pin is rated for a maximum dc voltage of 15
volts. An internal shunt diode is included for applications
where the voltage may exceed 15 volts. For voltages
greater than 15 volts an external shunt resistor must be
added in series with the Vcc pin. This resistor must be sized
such that at low line, the voltage drop across it will allow
for an input voltage of greater than that of the output of the
LDO and at high line such that the current into the chip does
not exceed its power rating.
LDO
NIS6201
Pwr GND
Sig GND
Comp
4
Vset
8
3
6
V reg
0.1uF
Vbias
The internal LDO contains a P−Channel FET and error
amplifier with a 0.5 volt reference. A voltage divider is
required from the Vreg pin to the comp pin to set the output
of the LDO. This output voltage (Vreg) is the voltage used
for the charge pump oscillator. The divider can be
calculated from the following formulas:
Rbias
+
0.50 V
Ibias
Figure 6. Bias Voltage Divider
Overcharge Comparator
Ibias is generally in the range of 100
mA
to 1 mA and sets
the bias current in the divider.
Rset
+
Rbias(Vreg
*
0.50 V)
0.50 V
The overcharge comparator provides a protection
function from an overvoltage condition at turn−on.
Figure 7 shows a typical configuration for this charge
pump. At turn−on there is a voltage divider consisting of
two capacitors and two diodes. If this device is being
operated at voltages significantly above the Vreg level, it
is possible to charge the Vreg cap well beyond its intended
level.
V
CC
1.25 V
+
−
Regulator
+
−
0.10 V
Overcharge
1 MHz
Oscillator
DRIVE
COMP
V
REG
GND
Figure 7. Overcharge Circuit
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