NIS5101
SMART HotPlugt IC/Inrush
Limiter/Circuit Breaker
The SMART HotPlug Integrated Circuit combines the control
function and power FET into a single IC that saves design time and
reduces the number of components required for a complete hot swap
application. It is designed to allow safe insertion and removal of
electronic equipment to −48 V backplanes. This chip features
simplicity of use combined with an integrated solution.
The SMART HotPlug includes user selectable undervoltage and
overvoltage lockout levels. It also has adjustable current limiting that
can be reduced from the maximum level with a single resistor.
Operation at the maximum current level requires no extra external
components. An internal temperature shutdown circuit greatly
increases the reliability of this device.
Features
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MARKING
DIAGRAM
8
1
7
S−PAK
EX SUFFIX
CASE 553AA
NIS5101EX
AYWWG
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated Power Device
100 V Operation
Thermal Limit Protection
Adjustable Current Limit
No External Current Shunt Required
Undervoltage and Overvoltage Lockouts
6.5 A Continuous Operation
UIS Rated
Main/Mirror MOSFET Current Ratio 820:1
Pb−Free Packages are Available
VoIP (Voice over Internet Protocol) Servers
−48 V Telecom Systems
+24 V Wireless Base Station Power
Central Office Switching
Electronic Circuit Breaker
7 Input +
= 1 for Thermal Latch or
2 for Thermal Auto−retry
A
= Assembly Location
Y
= Year
WW = Work Week
G = Pb−Free Device
X
ORDERING INFORMATION
Device
NIS5101E1T1
NIS5101E1T1G
Package
S−PAK
Latch Off
S−PAK
Latch Off
(Pb−Free)
S−PAK
Auto−Retry
S−PAK
Auto−Retry
(Pb−Free)
Shipping
†
2000 Units/Reel
2000 Units/Reel
Typical Applications
NIS5101E2T1
NIS5101E2T1G
2000 Units/Reel
2000 Units/Reel
Voltage
Regulator
Thermal
Shutdown
4, 8
Drain
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
6
UVLO/
ENABLE
Undervoltage
Lockout
5
OVLO
Overvoltage
Shutdown
Current
Limit
3
Current
Limit
Input −
1, 2
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 21
Publication Order Number:
NIS5101/D
NIS5101
PIN FUNCTION DESCRIPTION
Pin
1, 2
3
4, 8
5
6
7
Symbol
Input −
Current Limit
Drain
OVLO
UVLO/ENABLE
Input +
Description
Negative input voltage to the device. This is used as the internal reference for the IC.
This pin is shorted to the Input − pin for maximum current limit setting. If a reduced current limit level is
desired, a series resistor is added between this pin and the Input − pin.
Drain of power FET, which is also the switching node for the load.
The overvoltage shutdown point is programmed by a resistor from this pin to the Input + supply.
A resistor from Input + to the UVLO pin adjusts the voltage at which the device will turn on. An open drain
device can be connected to this pin, which will inhibit operation, when in its low impedance state.
Positive input voltage to the device.
MAXIMUM RATINGS
Rating
Input Voltage, Operating (Input + to Input −)
Transient (1 second)
Steady−State
Drain Voltage, Operating (Drain to Input −)
Transient (1 second)
Steady−State
Drain Current, Continuous (T
A
= 25°C, 2.0 in
2
Cu, double−sided board, 1 oz.)
Operating Temperature Range
Non−Operating Temperature Range
Lead Temperature, Soldering (10 Seconds)
Drain Current, Peak (Internally Limited)
Thermal Resistance, Junction−to−Air
0.5 in
2
copper
1.0 in
2
copper
Power Dissipation @ T
A
= 25°C
0.5 in
2
copper
1.0 in
2
copper
ESD Immunity for Device Handling (All Pins)
ESD Immunity Board Level (Note 1)
Lightning, Surge (8 x 20
msec)
(Note 1)
Symbol
V
in
−0.3 to 110
−0.3 to 100
V
DD
−0.3 to 110
−0.3 to 100
I
Davg
T
j
T
j
T
L
I
pk
R
qJA
75
43
P
max
1.4
2.4
HBM
JESD22−A114−B
IEC 61000−4−2
(Level 3)
IEC 61000−4−5
(Level 3)
2.0
6.0
2.0
48
kV
kV
kV
A
W
6.5
−40 to 145
−55 to 175
260
20
A
°C
°C
°C
A
°C/W
V
Value
Unit
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Applied between Input + and Input − pins only, and using an external 68 V bi−directional TVS device (P6SMB68AT3) connected across these
pins.
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2
NIS5101
ELECTRICAL CHARACTERISTICS
(T
j
= 25°C unless otherwise noted.)
Characteristic
POWER FET
Charging Time (Turn−On to Rated Max Current)
ON Resistance
Zero Gate Voltage Drain Current
(V
DS
= 100 V
dc
, V
GS
= 0 V
dc
)
Sense Voltage Tolerance (V
input
= 48 V, RextI
LIMIT
= 20
W)
Output Capacitance (V
DS
= 48 V
dc
, V
GS
= 0 V
dc
, f = 10 kHz)
THERMAL LIMIT
Shutdown Junction Temperature (Note 4)
Hysteresis (Note 4)
OVER/UNDERVOLTAGE
Turn−On Voltage (Rext
UVLO
=
R)
Hysteresis (Rext
UVLO
=
R)
Turn−On Voltage (Rext
UVLO
= 270 kW)
Hysteresis (Rext
UVLO
= 270 kW)
Zener Voltage (UVLO Pin Voltage at Turn−On)
OVLO Threshold (Input + Increasing, Rext
OVLO
=
R)
OVLO Threshold (Input + Increasing, Rext
OVLO
= 300 kW)
OVLO Hysteresis (Input + Decreasing, Rext
OVLO
= 300 kW)
CURRENT LIMIT
Short Circuit Current Limit (RextI
LIMIT
= 20
W)
(Note 5)
Overload Current Limit (RextI
LIMIT
= 20
W)
(Notes 4 and 5)
TOTAL DEVICE
Bias Current (Operational) (V
input
= 48 V, R
UVLO
=
R)
Bias Current (Non−Operational) (V
input
= 30 V, R
UVLO
=
R)
Minimum Operating Voltage (R
UVLO
= 30 kW)
2.
3.
4.
5.
I
Bias
I
Bias
Vin
min
−
−
−
1.4
800
18
−
−
−
mA
mA
V
I
LIM1
I
LIM2
3.5
5.4
4.2
6.0
5.0
6.6
A
A
V
on
V
hyst
V
on
V
hyst
V
Z
V
OV
V
OV
V
OVhyst
41.5
6.3
29
3.5
14.3
100
65
3.0
46
8.0
33
5.0
16
−
74
4.7
50.5
9.7
37
6.5
17.5
−
83
6.4
V
V
V
V
V
V
V
V
T
SD
T
hyst
125
35
135
40
145
45
°C
°C
t
chg
R
DSon
I
DSS
V
Sense
−
−
−
−
−
−
5.0
43
10
3.0
326
−
50
−
−
−
ms
mW
mA
%
pF
Symbol
Min
Typ
Max
Unit
Pulse Test: Pulse width 300
ms,
duty cycle 2%.
Switching characteristics are independent of operating junction temperatures.
Verified by design.
Please refer to explanation about the device’s current limit operation in short circuit and overload conditions.
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3
NIS5101
TYPICAL PERFORMANCE CURVES
(T
A
= 25°C unless otherwise noted)
100
45
Turn−On −40°C
40
Overload −40°C
10
I
Limit
(A)
Overload 25°C
Overload 120°C
Short Circuit −40°C
1
Short Circuit 25°C
Short Circuit 120°C
UVLO TRIP POINT (V)
35
30
25
Turn−Off −40°C
20
0.1
1
15
10
Turn−Off 25°C
Turn−Off 120°C
10
R
ext
_I
Limit
(W)
100
1000
100
UVLO_R
ext
(kW)
1000
Turn−On 25°C
Turn−On 120°C
Figure 2. Current Limit Adjustment
(For Main/Mirror MOSFET Current Ratio explanation,
see page 11)
100
90
OVLO TRIP POINT (V)
80
70
60
Turn−On 25°C
50
40
30
20
10
100
OVLO_R
ext
(kW)
1000
OVLO TRIP POINT (V)
Turn−Off 25°C
100
90
Figure 3. UVLO Adjustment
Turn−Off 120°C
80
70
60
50
40
30
20
10
100
OVLO_R
ext
(kW)
1000
Turn−On 120°C
Figure 4. OVLO Adjustment, T
J
= 255C
100
90
Turn−Off −40°C
OVLO TRIP POINT (V)
80
70
60
Turn−On −40°C
50
40
30
20
10
100
OVLO_R
ext
(kW)
1000
CASE TEMPERATURE (°C)
115
105
95
85
75
65
55
45
35
25
1
Figure 5. OVLO Adjustment, T
J
= 1205C
0.5 in
2
Cu area
1 in
2
Cu area
2 in
2
Cu area
Device Reaching
Thermal Shutdown
2
3
4
5
6
7
CONTINUOUS CURRENT (A)
Figure 6. OVLO Adjustment, T
J
= −405C
Figure 7. Continuous Current vs. Case Temperature
(Test performed on a double sided copper board, 1 oz)
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4
NIS5101
TYPICAL APPLICATION CIRCUIT & OPERATION WAVEFORMS
(T
A
= 25°C unless otherwise noted)
R
UVLO
Input +
UVLO/EN
NIS5101
Drain
OVLO
Current
Limit
Input −
+
DC−DC
Converter
+
+
R
OVLO
R
limit
Figure 8. Typical Application
Load Capacitor
470
mF
GND
Bounce
Bus Voltage
Load
Voltage
Load
Current
1 A/div
−48 V
Figure 9. Turn On Waveforms for 470
mF
Load Capacitor
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5
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