NBSG16VS
2.5V/3.3V SiGe Differential
Receiver/Driver with
Variable Output Swing
Description
1
QFN−16
MN SUFFIX
CASE 485G
Features
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency up to 12 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
40 ps Typical Rise and Fall Times (V
CTRL
= V
CC
−
1 V)
120 ps Typical Propagation Delay (V
CTRL
= V
CC
−
1 V)
Variable Swing PECL Output with Operating Range: V
CC
= 2.375 V to
3.465 V with V
EE
= 0 V
Variable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
=
−2.375
V to
−3.465
V
Output Level (100 mV to 750 mV Peak−to−Peak Output;
V
CC
−
V
EE
= 3.0 V to 3.465 V), Differential Output Only
50
W
Internal Input Termination Resistors
Compatible with Existing 2.5 V/3.3 V EP Devices
V
BB
and V
MM
Reference Voltage Output
Pb−Free Packages are Available
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
September, 2008
−
Rev. 12
1
Publication Order Number:
NBSG16VS/D
ÇÇ
ÇÇ
ÇÇ
The NBSG16VS is a differential receiver/driver targeted for high
frequency applications that require variable output swing. The device
is functionally equivalent to the EP16VS device with much higher
bandwidth and lower EMI capabilities. This device may be used for
applications driving VCSEL lasers.
Inputs incorporate internal 50
W
termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. The output amplitude is varied by applying a voltage
to the V
CTRL
input pin. Outputs are variable swing ECL from 100 mV
to 750 mV amplitude, optimized for operation from
V
CC
−
V
EE
= 3.0 V to 3.465 V.
The V
BB
and V
MM
pins are internally generated voltage supplies
available to this device only. The V
BB
is used as a reference voltage
for single−ended NECL or PECL inputs and the V
MM
pin is used as a
reference voltage for LVCMOS inputs. For single−ended input
operation, the unused complementary differential input is connected to
V
BB
or V
MM
as a switching reference voltage. V
BB
or V
MM
may also
rebias AC−coupled inputs. When used, decouple V
BB
and V
MM
via a
0.01
mF
capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
and V
MM
outputs should be left open.
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MARKING DIAGRAMS*
SGS
16
ALYWG
G
FCBGA−16
BA SUFFIX
CASE 489
16
SG
16VS
ALYWG
G
NBSG16VS
1
A
V
EE
2
NC
3
V
CTRL
4
V
EE
V
EE
16
VTD
1
2
V
BB
V
MM
15
14
V
EE
13
12
11
Exposed Pad (EP)
V
CC
Q
Q
V
CC
B
D
VTD
V
CC
Q
D
D
VTD
NBSG16VS
C
D
VTD
V
CC
Q
3
4
5
V
EE
6
7
8
10
9
D
V
EE
V
BB
V
MM
V
EE
NC V
CTRL
V
EE
Figure 1. BGA−16 Pinout
(Top View)
Figure 2. QFN−16 Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin
BGA
C2
C1
QFN
1
2
Name
VTD
D
I/O
−
ECL, CML,
LVCMOS,
LVDS,
LVTTL
Input
ECL, CML,
LVCMOS,
LVDS,
LVTTL
Input
−
−
−
Description
Internal 50
W
Termination Pin. See Table 2.
Inverted Differential Input. Internal 75 kW to V
EE
and 36.5 kW to V
CC
.
B1
3
D
Noninverted Differential Input. Internal 75 kW to V
EE
.
B2
A1,D1,A4,
D4
A2
A3
B3,C3
B4
C4
D3
D2
N/A
4
5,8,13,16
6
7
9,12
10
11
14
15
−
VTD
V
EE
NC
V
CTRL
V
CC
Q
Q
V
MM
V
BB
EP
Internal 50
W
Termination Pin. See Table 2.
Negative Supply Voltage
No Connect
Output Amplitude Swing Control. Bypass Pin to V
CC
through 0.1
mF
Capacitor.
−
RSECL
Output
RSECL
Output
−
−
−
Positive Supply Voltage
Noninverted Differential Output. Typically Terminated with 50
W
to
V
TT
= V
CC
−
2 V
Inverted Differential Output. Typically Terminated with 50
W
to V
TT
= V
CC
−
2 V
LVCMOS Reference Voltage Output. (V
CC
−
V
EE
)/2
ECL Reference Voltage Output
The Exposed Pad (EP) and the QFN−16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is not electrically connected to the
die but may be electrically and thermally connected to V
EE
on the PC board.
1. The NC pin is electrically connected to the die and must be left open.
2. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat−sinking conduit.
3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self−oscillation.
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2
NBSG16VS
V
CC
+
V
CTRL
0.1
mF
V
CTRL
VTD
50
W
D
D
50
W
VTD
V
EE
75
KW
75
KW
V
CC
36.5
KW
Q
Q
50
W
V
BB
V
CC
−
2 V
V
MM
VTD
50
W
Q OUT
Q OUT
50
W
VTD
V
EE
D
D
50
W
75
KW
75
KW
36.5
KW
Q
V
MM
R
VAR
V
CTRL
V
CC
+3.3 V
Q OUT
Q OUT
140
W
140
W
Q
V
BB
Figure 3. Logic Diagram/
Voltage Source Implementation
Figure 4. Alternative Voltage Source Implementation
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CML
LVDS
AC−COUPLED
RSECL, PECL, NECL
LVTTL
CONNECTIONS
Connect VTD and VTD to V
CC
Connect VTD and VTD Together
Bias VTD and VTD Inputs within
Common Mode Range (V
IHCMR
)
Standard ECL Termination Techniques
An external voltage should be applied to the unused
complementary differential input. Nominal voltage is
1.5 V for LVTTL.
V
MM
should be connected to the unused
complementary differential input.
LVCMOS
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3
NBSG16VS
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor (D, D)
Internal Input Pullup Resistor (D)
ESD Protection
Moisture Sensitivity (Note 4)
FCBGA−16
QFN−16
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
4. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Pb Pkg
Level 3
Level 1
Value
75 kW
36.5 kW
> 2 kV
> 100 V
Pb−Free Pkg
Level 3
Level 1
UL 94 V−0 @ 0.125 in
192
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
INPP
I
OUT
I
IN
I
BB
I
MM
T
A
T
stg
q
JA
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Differential Input Voltage
Output Current
Input Current Through R
T
(50
W
Resistor)
V
BB
Sink/Source
V
MM
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 5)
0 lfpm
500 lfpm
0 lfpm
500 lfpm
2S2P (Note 5)
2S2P (Note 6)
FCBGA−16
FCBGA−16
QFN−16
QFN−16
FCBGA−16
QFN−16
|D
−
D|
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
V
CC
−
V
EE
w
2.8 V
V
CC
−
V
EE
t
2.8 V
Continuous
Surge
Static
Surge
V
I
v
V
CC
V
I
w
V
EE
Condition 2
Rating
3.6
−3.6
3.6
−3.6
2.8
|V
CC
−
V
EE
|
25
50
45
80
1
1
−40
to +85
−65
to +150
108
86
41.6
35.2
5.0
4.0
225
265
Unit
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
°C
°C
°C/W
q
JC
T
sol
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
5. JEDEC standard 51−6 multilayer board
−
2S2P (2 signal, 2 power).
6. JEDEC standards multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG16VS
Table 5. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT
V
CC
= 2.5 V; V
EE
= 0 V (Note 7)
−40°C
Symbol
I
EE
V
OH
V
OL
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
(Max Swing)
(V
CTRL
= V
CC
−
600 mV)
Input HIGH Voltage
(Single−Ended) (Notes 10 and 11)
Input LOW Voltage
(Single−Ended) (Notes 10 and 12)
PECL Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Note 9)
(Differential Configuration)
CMOS Output Voltage Reference
(V
CC
−
V
EE
)/2
Internal Input Termination Resistor
Input HIGH Current (@ V
IH
)
Input LOW Current (@ V
IL
)
645
1090
V
THR
+ 75
V
IH
−
2500
1080
1.2
765
1210
V
CC
−
1000*
V
CC
−
1400*
1140
885
1330
V
CC
V
THR
−
75
1200
2.5
605
1035
V
THR
+ 75
V
IH
−
2500
1080
1.2
725
1155
V
CC
−
1000*
V
CC
−
1400*
1140
845
1275
V
CC
V
THR
−
75
1200
2.5
600
1010
V
THR
+ 75
V
IH
−
2500
1080
1.2
720
1130
V
CC
−
1000*
V
CC
−
1400*
1140
840
1250
V
CC
V
THR
−
75
1200
2.5
mV
mV
mV
V
Min
18
1315
Typ
25
1440
Max
32
1565
Min
18
1305
25°C
Typ
25
1430
Max
32
1555
Min
18
1305
85°C
Typ
25
1430
Max
32
1555
Unit
mA
mV
mV
V
IH
V
IL
V
BB
V
IHCMR
V
MM
R
TIN
I
IH
I
IL
mV
1100
45
1250
50
30
25
1400
55
100
50
1100
45
1250
50
30
25
1400
55
100
50
1100
45
1250
50
30
25
1400
55
100
50
W
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
7. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to
−0.965
V.
8. All loading with 50
W
to V
CC
−
2.0 V. V
OH
/V
OL
measured at V
IH
/V
IL
.
9. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
10. V
THR
is the voltage applied to the complementary input, typically V
BB
or V
MM
. V
THR(MIN)
= V
IHCMR
+ 75 mV. V
THR(MAX)
= V
IHCMR
−
75 mV.
11. V
IH
cannot exceed V
CC
.
12. V
IL
always
w
V
EE
.
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