Sets the drive strength of the output drivers and feedback inputs to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or eHSTL/HSTL (LOW)
compatible. Used in conjuction with V
DDQ
to set the interface levels.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock (has internal pull-up).
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank. (See Control Summary table.)
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on the feedback bank (See Control Summary table)
Selects appropriate oscillator circuit based on anticipated frequency range (See VCO Frequency Range Select table)
3-level inputs for feedback input divider selection (See Divide Selection table)
PLL enable/disable control. Set LOW for normal operation. When
PLL_EN
is HIGH, the PLL is disabled and REF
[1:0]
goes to all outputs.
Power down control. When
PD
is LOW, the inputs are disabled and internal switching is stopped. OMODE selects whether the outputs
are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/
HIGH, the nQ and QFB are stopped in a HIGH/LOW state, while the
nQ
and
QFB
are stopped in a LOW/HIGH state. When OMODE
is LOW, the outputs are tri-stated. Set
PD
HIGH for normal operation.
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the
inputs. The output will be 2.5V LVTTL.
Output disable control. Determines the outputs' disable state. Used in conjunction with
nsOE
and
PD.
(See Output Enable/Disable and
Powerdown tables.)
Power supply for output buffers. When using 2.5V LVTTL, V
DDQ
should be connected to V
DD.
Power supply for phase locked loop, lock output, inputs, and other internal circuitry
Ground
QFB
QFB
nQ
nQ
RxS
TxS
PE
nF
[2:1]
FBF
[2:1]
FS
DS
[1:0]
PLL_EN
PD
O
O
O
O
I
I
I
I
I
I
I
I
I
Adjustable
(2)
Adjustable
(2)
Adjustable
(2)
Adjustable
(2)
3-Level
(3)
3-Level
(3)
LVTTL
(1)
LVTTL
(1)
LVTTL
(1)
LVTTL
(1)
3-Level
(3)
LVTTL
(1)
LVTTL
(1)
LOCK
OMODE
V
DDQ
V
DD
GND
O
I
LVTTL
LVTTL
(1)
PWR
PWR
PWR
NOTES:
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V LVTTL signals as well.
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V
DDQ
voltage.
3. 3-level inputs are static inputs and must be tied to V
DD
or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
OUTPUT ENABLE/DISABLE
nsOE
L
H
H
OMODE
X
L
H
Output
Normal Operation
Tri-State
Gated
(1)
VCO FREQUENCY RANGE SELECT
FS
(1)
LOW
HIGH
Min.
50
100
Max.
125
250
Unit
MHz
MHz
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ
is stopped in a HIGH/LOW state while the
nQ
is stopped at a LOW/HIGH state.
POWERDOWN
PD
H
L
L
OMODE
X
L
H
Output
Normal Operation
Tri-State
Gated
(1)
NOTE:
1. The level to be set on FS is determined by the nominal operating frequency of the
VCO. The VCO frequency (F
NOM
) always appears at nQ and
nQ
outputs when they
are operated in their undivided modes. The frequency appearing at the REF
[1:0]
and
REF
[1:0]
/V
REF[1:0]
and FB and
FB/V
REF
2 inputs will be F
NOM
when the QFB and
QFB
are undivided and DS
[1:0]
= MM. The frequency of REF
[1:0]
and
REF
[1:0]
/V
REF[1:0]
and FB and
FB/V
REF
2 inputs will be F
NOM
/2 or F
NOM
/4 when the part is configured for
frequency multiplication by using a divided QFB and
QFB
and setting DS
[1:0]
= MM.
Using the DS
[1:0]
inputs allows a different method for frequency multiplication (see
Divide Selection table).
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ
and QFB are stopped in a HIGH/LOW state, while the
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