NBSG11
2.5V/3.3V SiGe 1:2
Differential Clock Driver
with RSECL* Outputs
*Reduced Swing ECL
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Description
MARKING DIAGRAM*
1
QFN16
MN SUFFIX
CASE 485G
A
L
Y
W
G
Features
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency
up to
12 GHz Typical
Maximum Input Data Rate
up to
12 Gb/s Typical
30 ps Typical Rise and Fall Times
125 ps Typical Propagation Delay
RSPECL Output with Operating Range: V
CC
= 2.375 V to 3.465 V
with V
EE
= 0 V
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
RSECL Output Level (400 mV Peak−to−Peak Output), Differential
Output Only
50
W
Internal Input Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
These are Pb−Free Devices
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
June, 2014 − Rev. 17
Publication Order Number:
NBSG11/D
ÇÇ
ÇÇ
1
The NBSG11 is a 1−to−2 differential fanout buffer, optimized for
low skew and Ultra−Low JITTER.
Inputs incorporate internal 50
W
termination resistors and accept
Negative ECL (NECL), Positive ECL (PECL), CML, LVCMOS,
LVTTL, or LVDS. Outputs are Reduced Swing ECL (RSECL),
400 mV. All outputs loaded with 50
W
to V
CC
− 2 V.
16
SG
11
ALYWG
G
NBSG11
V
EE
16
VTCLK
CLK
CLK
VTCLK
NC
15
NC
14
V
CC
13
Exposed Pad (EP)
1
2
NBSG11
3
4
12
11
10
9
Q0
Q0
Q1
Q1
5
V
EE
6
NC
7
NC
8
V
CC
Figure 1. QFN16 Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
Name
VTCLK
CLK
I/O
−
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
−
−
−
−
RSECL Output
RSECL Output
RSECL Output
RSECL Output
−
Description
Internal 50
W
Termination Pin. See Table 2.
Inverted Differential Input. Internal 75 kW to V
EE
and 36.5 kW to V
CC
.
3
CLK
Noninverted Differential Input. Internal 75 kW to V
EE
.
4
5,16
6,7,14,15
8,13
9
10
11
12
−
VTCLK
V
EE
NC
V
CC
Q1
Q1
Q0
Q0
EP
Internal 50
W
Termination Pin. See Table 2.
Negative Supply Voltage
No Connect
Positive Supply Voltage
Inverted Differential Output 1. Typically Terminated with 50
W
to V
TT
= V
CC
− 2.0 V.
Noninverted Differential Output 1. Typically Terminated with 50
W
to V
TT
= V
CC
− 2.0 V.
Inverted Differential output 0. Typically Terminated with 50
W
to V
TT
= V
CC
− 2.0 V.
Noninverted Differential Output 0. Typically Terminated with 50
W
to V
TT
= V
CC
− 2.0 V.
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is not electrically connected to the die but may be electrically
and thermally connected to V
EE
on the PC board.
1. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat−sinking conduit.
2. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and
if no signal is applied then the device will be susceptible to self−oscillation.
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NBSG11
V
CC
VTCLK
36.5 KW
50
W
CLK
CLK
50
W
VTCLK
V
EE
75 KW
75 KW
Q0
Q0
Q1
Q1
Figure 2. Logic Diagram
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CML
LVDS
AC−COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
CONNECTIONS
Connect VTCLK and VTCLK to V
CC
Connect VTCLK and VTCLK together
Bias VTCLK and VTCLK Inputs within
(VIHCMR) Common Mode Range
Standard ECL Termination Techniques
An external voltage should be be applied to the
unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and V
CC
/2
for LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor (CLK, CLK)
Internal Input Pullup Resistor (CLK)
ESD Protection
Moisture Sensitivity (Note 3)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
Pb−Free
Oxygen Index: 28 to 34
Value
75 kW
36.5 kW
> 2 kV
> 100 V
Level 1
UL 94 V−0 @ 0.125 in
125
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NBSG11
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
INPP
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Differential Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 4)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
2S2P (Note 4)
|D − D|
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
V
CC
− V
EE
w
V
CC
− V
EE
<
Continuous
Surge
2.8 V
2.8 V
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
3.6
−3.6
3.6
−3.6
2.8
|V
CC
− V
EE
|
25
50
−40 to +85
−65 to +150
41.6
35.2
4.0
265
Unit
V
V
V
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG11
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT
V
CC
= 2.5 V; V
EE
= 0 V (Note 5)
−40°C
Symbol
Characteristic
Min
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
POWER SUPPLY CURRENT
I
EE
Negative Power Supply Current
45
60
75
45
60
75
45
60
75
mA
RSPECL OUTPUTS
(Note 6)
V
OH
V
OUTPP
Output HIGH Voltage
Output Voltage Amplitude
1450
350
1530
410
1575
525
1525
350
1565
410
1600
525
1550
350
1590
410
1625
525
mV
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED
(Figures 4 & 6) (Note 7)
V
IH
V
IL
V
th
V
ISE
Input HIGH Voltage
Input LOW Voltage
Input Threshold Reference Voltage
Range (Note 8)
Single−Ended Input Voltage (V
IH
–
V
IL
)
1200
0
950
150
V
CC
V
IH
−
150
V
CC
–75
2600
1200
0
950
150
V
CC
V
IH
−
150
V
CC
–75
2600
1200
0
950
150
V
CC
V
IH
−
150
V
CC
–75
260
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 5 & 7) (Note 9)
V
IHD
V
ILD
V
ID
V
IHCMR
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage
(V
IHD
– V
ILD
)
Input HIGH Voltage Common Mode
Range (Note 10) (Figure 8)
Input HIGH Current (@V
IH
)
Input LOW Current (@V
IL
)
1200
0
75
1200
80
25
V
CC
V
CC
−
75
2600
2500
150
100
1200
0
75
1200
80
25
V
CC
V
CC
−
75
2600
2500
150
100
1200
0
75
1200
80
25
V
CC
V
CC
−
75
2600
2500
150
100
mV
mV
mV
mV
mA
mA
W
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
.
6. All loading with 50
W
to V
CC
− 2 V.
7. Vth, V
IH
, V
IL,
and V
ISE
parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode. V
th
= (V
IH
− V
IL
) / 2.
9. V
IHD
, V
ILD,
V
ID
and V
IHCMR
parameters must be complied with simultaneously.
10. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differen-
tial input signal.
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