NB7L14M
2.5V/3.3V Differential 1:4
Clock/Data Fanout Buffer/
Translator with CML
Outputs and Internal
Termination
Description
http://onsemi.com
MARKING
DIAGRAM*
16
1
The NB7L14M is a differential 1−to−4 clock/data distribution chip
with internal source terminated CML output structures, optimized for
minimal skew and jitter. Device produces four identical output copies
of clock or data operating up to 8 GHz or 12 Gb/s, respectively. As
such, NB7L14M is ideal for SONET, GigE, Fiber Channel, Backplane
and other clock/data distribution applications.
Inputs incorporate internal 50
W
termination resistors and accept
LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6).
Differential 16 mA CML outputs provide matching internal 50
W
terminations, and 400 mV output swings when externally terminated
with 50
W
to V
CC
(See Figure 14).
The device is offered in a low profile 3x3 mm 16−pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
1
QFN−16
MN SUFFIX
CASE 485G
NB7L
14M
ALYWG
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency up to 8 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
< 0.5 ps of RMS Clock Jitter
< 10 ps of Data Dependent Jitter
30 ps Typical Rise and Fall Times
110 ps Typical Propagation Delay
6 ps Typical Within Device Skew
Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
CML Output Level (400 mV Peak−to−Peak Output) Differential
Output Only
•
50
W
Internal Input and Output Termination Resistors
•
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
•
These are Pb−Free Devices
V
TCLK
50
W
CLK
CLK
50
W
V
TCLK
Q0
Q0
Q1
Q1
Q2
Q2
Q3
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Figure 1. Logic Diagram
Q3
1
Publication Order Number:
NB7L14M/D
©
Semiconductor Components Industries, LLC, 2012
June, 2012
−
Rev. 6
NB7L14M
V
EE
16
V
TCLK
CLK
CLK
V
TCLK
1
2
NB7L14M
3
4
5
V
EE
6
Q3
7
Q3
8
V
CC
Q0
15
Q0
14
V
CC
Exposed Pad (EP)
13
12 Q1
11 Q1
10 Q2
9
Q2
Figure 2. QFN−16 Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
Name
V
TCLK
CLK
I/O
−
LVPECL, CML,
LVCMOS, LVTTL,
LVDS
LVPECL, CML,
LVCMOS, LVTTL,
LVDS
−
Power Supply
CML Output
CML Output
Power Supply
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
−
Internal 50
W
Termination Pin for CLK.
Inverted Differential Clock/Data Input. (Note 1)
Description
3
CLK
Non−inverted Differential Clock/Data Input. (Note 1)
4
5,16
6
7
8,13
9
10
11
12
14
15
−
V
TCLK
V
EE
Q3
Q3
V
CC
Q2
Q2
Q1
Q1
Q0
Q0
EP
Internal 50
W
Termination Pin for CLK.
Negative Supply Voltage. All V
EE
pins must be externally connected to a Power Supply to
guarantee proper operation.
Inverted Differential Output 3 with Internal 50
W
Source Termination Resistor. (Note 2)
Non−inverted Differential Output 3 with Internal 50
W
Source Termination Resistor. (Note 2)
Positive Supply Voltage. All V
CC
pins must be externally connected to a Power Supply to
guarantee proper operation.
Inverted Differential Output 2 with Internal 50
W
Source Termination Resistor. (Note 2)
Non−inverted Differential Output 2 with Internal 50
W
Source Termination Resistor. (Note 2)
Inverted Differential Output 1 with Internal 50
W
Source Termination Resistor. (Note 2)
Non−inverted Differential Output 1 with Internal 50
W
Source Termination Resistor. (Note 2)
Inverted Differential Output 0 with Internal 50
W
Source Termination Resistor. (Note 2)
Non−inverted Differential Output 0 with Internal 50
W
Source Termination Resistor. (Note 2)
Exposed Pad. Thermal pad on the package bottom must be attached to a heatsinking
conduit to improve heat transfer. It is recommended to connect the EP to the lower
potential (V
EE
).
1. In the differential configuration when the input termination pins (V
TCLK
, V
TCLK
) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK, then the device will be susceptible to self−oscillation.
2. CML outputs require 50
W
receiver termination resistors to V
CC
for proper operation.
http://onsemi.com
2
NB7L14M
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
QFN−16
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Level 1
Value
> 1500 V
> 50 V
> 500 V
Pb−Free Pkg
Level 1
Moisture Sensitivity (Note 3)
UL 94 V−0 @ 0.125 in
387
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
I
V
INPP
I
IN
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Input Voltage
Differential Input Voltage |CLK
−
CLK|
Input Current Through R
T
(50
W
Resistor)
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 4)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
2S2P (Note 4)
QFN−16
QFN−16
QFN−16
Condition 1
V
EE
= 0 V
V
EE
= 0 V
V
CC
−
V
EE
w
2.8 V
V
CC
−
V
EE
< 2.8 V
Static
Surge
Continuous
Surge
QFN−16
V
EE
v
V
I
v
V
CC
Condition 2
Rating
3.6
3.6
2.8
|V
CC
−
V
EE
|
45
80
25
50
−40
to +85
−65
to +150
42
36
3 to 4
265
265
Units
V
V
V
V
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power).
http://onsemi.com
3
NB7L14M
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs
(
V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V, T
A
=
−40°C
to +85°C)
(Note 5)
Symbol
I
CC
V
OH
V
OL
V
th
V
IH
V
IL
V
ISE
V
IHCLK
V
ILCLK
V
CMR
V
ID
I
IH
I
IL
R
TIN
R
TOUT
R
Temp Coef
Characteristic
Power Supply Current (Inputs and Outputs Open)
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
V
CC
−
60
V
CC
−
530
800
1200
V
EE
150
Min
Typ
140
V
CC
−
20
V
CC
−
420
Max
190
V
CC
V
CC
−
360
V
CC
−
75
V
CC
V
CC
−
150
2500
Unit
mA
mV
mV
Differential Input Driven Single−Ended
(see Figures 10 & 12) (Note 8)
Input Threshold Reference Voltage Range (Note 7)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Single−Ended Input Voltage (V
IH
– V
IL
)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration) (Note 10)
Differential Input Voltage (V
IHCLK
−
V
ILCLK
)
Input HIGH Current CLK / CLK (V
TCLK
/V
TCLK
Open)
Input LOW Current CLK / CLK (V
TCLK
/V
TCLK
Open)
Internal Input Termination Resistor
Internal Output Termination Resistor
Internal I/O Termination Resistor Temperature Coefficient
mV
mV
mV
mV
Differential Inputs Driven Differentially
(see Figures 11 & 13) (Note 9)
1200
V
EE
800
75
0
−10
45
45
25
0
50
50
6.38
V
CC
V
CC
−
75
V
CC
– 38
2500
100
10
55
55
mV
mV
mV
mV
mA
mA
W
W
mW/°C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
.
6. CML outputs require 50
W
receiver termination resistors to V
CC
for proper operation.
7. V
th
is applied to the complementary input when operating in single−ended mode. V
th
= (V
IH
−
V
IL
)/2.
8. Vth, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
10. V
CMR
min varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential input
signal.
http://onsemi.com
4
NB7L14M
Table 5. AC CHARACTERISTICS
(V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V; Note 11)
−40°C
Symbol
V
OUTPP
f
data
t
PLH
,
t
PHL
t
SKEW
Characteristic
Output Voltage Amplitude (@V
INPPmin
)
(See Figure 4)
Maximum Operating Data Rate
Propagation Delay to Output Differential
Duty Cycle Skew (Note 12)
Within−Device Skew
Device−to−Device Skew (Note 13)
f
in
= 6 GHz
f
in
= 8 GHz
Peak/Peak Data Dependent Jitter f
in
= 2.488 Gb/s
(Note 15)
f
data
= 5 Gb/s
f
data
= 10 Gb/s
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 16)
Output Rise/Fall Times @ 1 GHz
(20%
−
80%)
Q, Q
75
RMS Random Clock Jitter (Note 14)
f
in
≤
6 GHz
f
in
≤
8 GHz
Min
280
125
10
70
Typ
400
300
12
110
2.0
6.0
20
0.2
0.2
2.0
5.0
6.0
400
30
150
5.0
15
50
0.5
0.5
5.0
8.0
10
2500
60
75
Max
Min
280
125
10
70
25°C
Typ
400
300
12
110
2.0
6.0
20
0.2
0.2
2.0
5.0
6.0
400
30
150
5.0
15
50
0.5
0.5
5.0
8.0
10
2500
60
75
Max
Min
280
125
10
70
85°C
Typ
400
300
12
110
2.0
6.0
20
0.2
0.2
2.0
5.0
6.0
400
30
150
5.0
15
50
0.5
0.5
5.0
8.0
10
2500
60
Max
Unit
mV
Gb/s
ps
ps
t
JITTER
ps
V
INPP
t
r
t
f
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured by forcing V
INPP
(TYP) from a 50% duty cycle clock source. All loading with an external R
L
= 50
W
to V
CC
.
Input edge rates 40 ps (20%
−
80%).
12. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @1 GHz.
13. Device to device skew is measured between outputs under identical transition @ 1 GHz.
14. Additive RMS jitter with 50% duty cycle clock signal at 10 GHz.
15. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 2
^23
−1.
16. V
INPP
(MAX) cannot exceed V
CC
−
V
EE
. Input voltage swing is a single−ended measurement operating in differential mode.
450
OUTPUT VOLTAGE AMPLITUDE (mV)
400
350
300
250
200
150
100
50
0
1
2
3
V
CC
= 3.3 V
V
CC
= 2.5 V
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) at Ambient Temperature (Typical)
(V
INPP
= 400 mV)
http://onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
