NB6N239S
3.3 V, 3.0 GHz Any
Differential Clock IN to
LVDS OUT
÷1/2/4/8, ÷2/4/8/16
Clock Divider
Description
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MARKING DIAGRAM*
16
1
The NB6N239S is a high−speed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios;
B1/2/4/8
and
B2/4/8/16.
Both divider circuits drive LVDS compatible outputs.
(More device information on page 7). The NB6N239S is a member
of the ECLinPS MAX™ family of high performance clock products.
Features
1
Bottom View
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
•
•
•
•
•
•
•
•
•
•
•
•
•
•
NB6N
239S
ALYWG
G
Maximum Clock Input Frequency, 3.0 GHz (1.5 GHz with
B1)
Input Compatibility with LVDS/LVPECL/CML/HSTL/HCSL
Rise/Fall Time 120 ps Typical
< 5 ps Typical Within Device Output Skew
Example; 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Outputs
Internal 50
W
Termination Provided
Random Clock Jitter < 2 ps RMS
QA
B1
Edge Aligned to QB
Bn
Edge
Operating Range: V
CC
= 3.0 V to 3.465 V with GND = 0 V
Master Reset for Synchronization of Multiple Chips
V
BBAC
Reference Output
Synchronous Output Enable/Disable
TIA/EIA
−
644 Compliant
These Devices are Pb−Free and are RoHS Compliant
SELA0
SELA1
CLK
VT
CLK
V
BBAC
50
W
50
W
R
B2
B4
B
B8
B16
B1
B2
A
B4
B8
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
QA
QA
QB
QB
EN
SELB0
SELB1
MR
+
Figure 1. Simplified Logic Diagram
1
Publication Order Number:
NB6N239S/D
©
Semiconductor Components Industries, LLC, 2013
January, 2013
−
Rev. 6
NB6N239S
MR
16
VT
CLK
CLK
V
BBAC
1
2
NB6N239S
3
4
5
EN
6
7
8
10
9
SELA0 SELA1 V
CC
15
14
13
12
11
QA
QA
QB
QB
SELB0 SELB1 GND
Exposed Pad (EP)
Figure 2. Pinout: QFN−16
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
VT
CLK
CLK
V
BBAC
EN*
SELB0*
SELB1*
GND
QB
QB
QA
QA
V
CC
SELA1*
SELA0*
MR**
EP
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
Power Supply
LVDS Output
LVDS Output
LVDS Output
LVDS Output
Power Supply
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
Power Supply (OPT)
LVDS, LVPECL, CML,
HCSL, HSTL Input
LVDS, LVPECL, CML,
HCSL, HSTL Input
I/O
Description
Internal 100
W
Center−Tapped Termination Pin for CLK and CLK.
Noninverted Differential CLOCK Input.
Inverted Differential CLOCK Input.
Output Voltage Reference for Capacitor Coupled Inputs, only.
Synchronous Output Enable
Clock Divide Select Pin
Clock Divide Select Pin
Negative Supply Voltage
Inverted Differential Output. Typically terminated with 100
W
across differential outputs.
Noninverted Differential Output. Typically terminated with 100
W
across differential
outputs.
Inverted Differential Output. Typically terminated with 100
W
across differential outputs.
Noninverted Differential Output. Typically terminated with 100
W
across differential out-
puts.
Positive Supply Voltage.
Clock Divide Select Pin
Clock Divide Select Pin
Master Reset Asynchronous, Default Open High, Asserted LOW
The Exposed Pad on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The pad is electrically connected to the die, and
is recommended to be electrically and thermally connected to GND on the PC board.
*Pins will default LOW when left OPEN.
**Pins will default HIGH when left OPEN.
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2
NB6N239S
+
SELA0
V
CC
SELA1
B1
B2
B4
R
B8
CLK
VT
CLK
50
W
50
W
A
QA
QA
R
B2
B
EN
SELB0
SELB1
MR
V
BBAC
B4
B8
B16
QB
QB
+
GND
Figure 3. Logic Diagram
Table 2. FUNCTION TABLE
CLK
EN*
L
H
X
MR**
H
H
L
FUNCTION
Divide
Hold Q
Reset Q
X
Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS
SELA1*
L
L
H
H
SELA0*
L
H
L
H
QA Outputs
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Table 4. CLOCK DIVIDE SELECT, QB OUTPUTS
SELB1*
L
L
H
H
SELB0*
L
H
L
H
QB Outputs
Divide by 2
Divide by 4
Divide by 8
Divide by 16
= Low−to−High Transition
= High−to−Low Transition
X = Don’t Care
*Pins will default LOW when left OPEN.
**Pins will default HIGH when left OPEN.
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3
NB6N239S
Table 5. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Value
75 kW
75 kW
> 1500 V
> 100 V
> 1000 V
Pb−Free Pkg
QFN−16
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Oxygen Index: 28 to 34
Level 1
UL 94 V−0 @ 0.125 in
370
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Table 6. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
SC
Input Voltage
Output Short Circuit Current
TIA/EIA
−
644 Compliant
I
BBAC
T
A
T
stg
q
JA
q
JC
T
sol
V
BBAC
Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
Standard Board
Line−to−Line
Line−to−GND
Parameter
Positive Mode Power Supply
Condition 1
GND = 0 V
GND = 0 V
GND
v
V
I
v
V
CC
Condition 2
Rating
3.6
3.6
12
24
±
0.5
−40
to +85
−65
to +150
41.6
35.2
4.0
265
Unit
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
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4
NB6N239S
Table 7. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS
(V
CC
= 3.0 V to 3.465 V, GND = 0 V)
−405C
Symbol
I
CC
Characteristic
Power Supply Cur-
rent (Inputs and
Outputs OPEN)
Output HIGH
Voltage (Notes 2)
Output LOW
Voltage (Notes 2)
Differential Output
Voltage (Figure 21)
V
OD
Magnitude
Change
Offset Voltage
(Figure 21)
V
OS
Magnitude
Change
900
1600
900
450
50
1375
50
250
0
1125
0
450
50
1375
50
Min
Typ
Max
Min
35
255C
Typ
45
Max
55
Min
85°C
Typ
Max
Unit
mA
V
OH
V
OL
V
OD
DV
OD
V
OS
DV
OS
1600
900
250
0
1125
0
1600
mV
mV
250
0
1125
0
450
50
1375
50
mV
mV
mV
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(Figures 7, 10)
V
th
Input Threshold
Reference Voltage
(Note 3)
Single−ended Input
HIGH Voltage
Single−ended Input
LOW Voltage
Output Voltage Ref-
erence @ 100
mA
(Note 6)
V
CC
=
3.3 V
100
V
CC
−
100
100
V
CC
−
100
100
V
CC
−
100
mV
V
IH
V
IL
V
BBAC
V
th
+ 100
GND
V
CC
−1460
1840
V
CC
−
1330
1970
V
CC
V
th
−
100
V
CC
−1200
2100
V
th
+ 100
GND
V
CC
−1460
1840
V
CC
−
1340
1960
V
CC
V
th
−
100
V
CC
−1200
2100
V
th
+ 100
GND
V
CC
−1460
1840
V
CC
−
1350
1950
V
CC
V
th
−
100
V
CC
−1200
2100
mV
mV
mV
DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY
(Figures 8, 9, 11) (Note 5)
V
IHD
V
ILD
V
CMR
Differential Input
HIGH Voltage
Differential Input
LOW Voltage
Input Common
Mode Range (Dif-
ferential Cross−
point Voltage)
(Note 4)
Differential Input
Voltage (V
IHD(CLK)
−
V
ILD(CLK)
) and
(V
IHD(CLK)
−
V
ILD(CLK)
)
Internal Input Ter-
mination Resistor
100
GND
50
V
CC
V
CC
– 100
V
CC
– 50
100
GND
50
V
CC
V
CC
– 100
V
CC
– 50
100
GND
50
V
CC
V
CC
– 100
V
CC
– 50
mV
mV
mV
V
ID
100
V
CC
−
GND
100
V
CC
−
GND
100
V
CC
−
GND
mV
R
TIN
45
50
55
45
50
55
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Outputs loaded with 100
W
across LVDS outputs.
3. V
th
is applied to the complementary input when operating in single−ended mode.
4. VCMR
MIN
varies 1:1 with GND, VCMR
MAX
varies 1:1 with V
CC
.
5. Input and output voltage swing is a single−ended measurement operating in differential mode.
6. V
BBAC
used to rebias capacitor−coupled inputs only (see Figures 16 and 17).
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