NB100LVEP56
2.5V / 3.3V ECL DUAL
Differential 2:1 Multiplexer
Description
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
both LVECL and LVCMOS input voltage levels. Multiple V
BB
pins
are provided.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single−ended input operation, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
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MARKING
DIAGRAMS*
N100
VP56
ALYWG
G
TSSOP−20 WB
DT SUFFIX
CASE 948E
24
1
24
1
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
525 ps Typical Propagation Delays
Low Profile QFN Package
PECL Mode Operating Range:
V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= −2.375 V to −3.8 V
Separate, Common Select, and Individual Select
(Compatible with ECL and CMOS Input Voltage Levels)
Q Output Will Default LOW with Inputs Open or at V
EE
Multiple V
BB
Outputs
These Devices are Pb−Free and are RoHS Compliant
QFN24
MN SUFFIX
CASE 485L
A
L
Y
W
G
N100
VP56
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2016
1
February, 2016 − Rev. 11
Publication Order Number:
NB100LVEP56/D
NB100LVEP56
Table 1. PIN FUNCTION DESCRIPTION
ÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
TSSOP
14,20
11
QFN
3,9,18,19,
20
15,24
6,12
4
5
7
8
10
11
13
14
2
1
17
16
23
22
21
−
3,8
1
2
4
5
6
7
9
10
19
18
13
12
17
16
15
N/A
Pin No.
Name
V
CC
V
EE
V
BB0
,
V
BB1
D0a
D0a
D0b
D0b
D1a
D1a
D1b
D1b
Q0
Q0
Q1
Q1
SEL0
I/O
−
−
−
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Output
ECL Output
ECL Output
ECL Output
ECL, CMOS
Input
ECL, CMOS
Input
ECL, CMOS
Input
−
Default
State
−
−
−
Low
High
Low
High
Low
High
Low
High
−
−
−
−
Low
Low
Low
Description
Positive Supply Voltage. All VCC Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
Negative Supply Voltage. All VEE Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
ECL Reference Voltage Output
Noninverted Differential Data a Input to MUX 0. Internal 75 kW to
V
EE
.
Inverted Differential Data a Input to MUX 0. Internal 75 kW to V
EE
and 37 kW to V
CC
.
Noninverted Differential Data b Input to MUX 0. Internal 75 kW to
V
EE
.
Inverted Differential Data b Input to MUX 0. Internal 75 kW to V
EE
and 37 kW to V
CC
.
Noninverted Differential Data a Input to MUX 1. Internal 75 kW to
V
EE
.
Inverted Differential Data a Input to MUX 1. Internal 75 kW to V
EE
and 37 kW to V
CC
.
Noninverted Differential Data b Input to MUX 1. Internal 75 kW to
V
EE
.
Inverted Differential Data b Input to MUX 1. Internal 75 kW to V
EE
and 37 kW to V
CC
.
Noninverted Differential Output MUX 0. Typically Terminated with
50
W
to V
TT
= V
CC
− 2.0 V.
Inverted Differential Output MUX 0. Typically Terminated with
50
W
to V
TT
= V
CC
− 2.0 V.
Noninverted Differential Output MUX 1. Typically Terminated with
50
W
to V
TT
= V
CC
− 2.0 V.
Inverted Differential Output MUX 1. Typically Terminated with
50
W
to V
TT
= V
CC
− 2.0 V.
Noninverted Differential Select Input to MUX 0. Internal 75 kW to
V
EE
.
Noninverted Differential Common Select Input to Both MUX.
Internal 75 kW to V
EE
.
Noninverted Differential Select Input to MUX 1. Internal 75 kW to
V
EE
.
Exposed Pad. The exposed pad (EP) on the package bottom
must be attached to a heat−sinking conduit. The exposed pad
may only be electrically connected to V
EE
.
COM_SEL
SEL1
EP
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NB100LVEP56
D0a
R
1
D0a
R
1
D0b
R
1
R
2
D0b
R
1
D1a
R
1
D1a
R
1
D1b
R
1
R
2
D1b
R
1
R
2
R
1
COM_SEL
R
1
SEL1
1
R
1
Q1
Q1
0
V
CC
V
EE
R
2
1
Q0
Q0
0
SEL0
Table 2. TRUTH TABLE
SEL0
X
L
L
H
H
SEL1
X
L
H
H
L
COM_SEL
H
L
L
L
L
Q0, Q0
a
b
b
a
a
Q1, Q1
a
b
a
a
b
Figure 1. Logic Diagram
COM_SEL
COM
V
EE
SEL0 SEL SEL1 V
CC
V
CC
24
23
22
21
20
19
Exposed Pad
(EP)
SEL0
SEL1
V
CC
V
CC
V
EE
Q0
Q0
Q1
Q1
Q0
Q0
V
CC
1
2
3
NB100LVEP56
4
5
6
7
8
9
10
11
12
18
17
16
15
14
13
V
CC
Q1
Q1
V
EE
D1b
D1b
20
19
18
17
16
15
14
13
12
11
NB100LVEP56
D0a
D0a
1
D0a
2
D0a
3
V
BBO
4
D0b
5
D0b
6
D1a
7
D1a
8
V
BB1
9
D1b
10
D1b
V
BB0
Figure 2. TSSOP−20 Lead Pinout
(Top View)
D0b D0b V
CC
D1a D1a V
BB1
Figure 3. QFN−24 Lead Pinout
(Top View)
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
(R1)
(R2)
Human Body Model
Machine Model
Charged Device Model
TSSOP−20
QFN−24
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Value
75 kW
37 kW
> 2 kV
> 150 V
> 2 kV
Pb−Free Pkg
Level 1
Level 1
UL 94 V−0 @ 0.125 in
354 Devices
Moisture Sensitivity (Note 1)
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NB100LVEP56
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JA
Parameter
Positive Mode Power Supply
Negative Mode Power Supply
Positive Mode Input Voltage
Negative Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
JEDEC 51−3 (1S − Single Layer Test Board)
Thermal Resistance (Junction−to−Ambient)
JEDEC 51−6 (2S2P−Multi Layer Test Board)
with Filled Thermal Vias
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
0 lfpm
500 lfpm
Standard Board
TSSOP−20
TSSOP−20
QFN−24
QFN−24
TSSOP−20
QFN−24
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
v
V
CC
V
I
w
V
EE
Condition 2
Rating
6
−6
6
−6
50
100
"0.5
−40 to +85
−65 to +150
140
50
37
32
23 to 41
11
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C
q
JC
T
sol
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 5. DC CHARACTERISTICS, PECL
V
CC
= 2.5 V, V
EE
= 0 V (Note 2)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
I
IH
I
IL
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs) (Note 4)
Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs) (Note 4)
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 5)
Input HIGH Current (@V
IH
)
Input LOW Current (@V
IL
)
D
D
SEL
0.5
−150
−150
Min
35
1355
555
1335
1335
V
EE
555
1.2
Typ
45
1480
775
Max
55
1605
900
V
CC
1620
875
875
2.5
150
0.5
−150
−150
Min
35
1355
555
1335
1335
V
EE
555
1.2
25°C
Typ
45
1480
775
Max
55
1605
900
V
CC
1620
875
875
2.5
150
0.5
−150
−150
Min
35
1355
555
1275
1275
V
EE
555
1.2
85°C
Typ
48
1480
775
Max
58
1605
900
V
CC
1620
875
875
2.5
150
Unit
mA
mV
mV
mV
mV
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary −0.125 V to +1.3 V.
3. All loading with 50
W
to V
CC
− 2.0 V.
4. Do not use V
BB
at V
CC
< 3.0 V.
5. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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NB100LVEP56
Table 6. DC CHARACTERISTICS, PECL
V
CC
= 3.3 V, V
EE
= 0 V (Note 6)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs)
Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs)
Output Reference Voltage (Note 8)
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
Input HIGH Current (@V
IH
)
Input LOW Current (@V
IL
)
D
D
SEL
0.5
−150
−150
Min
35
2155
1355
2135
2135
V
EE
1355
1775
1.2
1875
Typ
45
2280
1575
Max
55
2405
1700
V
CC
2420
1675
1675
1975
3.3
150
0.5
−150
−150
Min
35
2155
1355
2135
2135
V
EE
1355
1775
1.2
1875
25°C
Typ
45
2280
1575
Max
55
2405
1700
V
CC
2420
1675
1675
1975
3.3
150
0.5
−150
−150
Min
35
2155
1355
2135
2135
V
EE
1355
1775
1.2
1875
85°C
Typ
48
2280
1575
Max
58
2405
1700
V
CC
2420
1675
1675
1975
3.3
150
Unit
mA
mV
mV
mV
mV
mV
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.5 V to −0.3 V.
7. All loading with 50
W
to V
CC
− 2.0 V.
8. Single−Ended input operation is limited to V
CC
w
3.0 V in PECL mode.
9. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
Table 7. DC CHARACTERISTICS, NECL
V
CC
= 0 V, V
EE
= −3.8 V to −2.375 V (Note 10)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
Input HIGH Voltage
(SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs)
Input LOW Voltage
(SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs)
Output Reference Voltage (Note 12)
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
Input HIGH Current (@V
IH
)
Input LOW Current (@V
IL
)
D
D
SEL
0.5
−150
−150
Min
35
−1145
−1945
−1165
−1165
V
EE
−1945
−1525
−1425
Typ
45
−1020
−1725
Max
55
−895
−1600
V
CC
−880
−1600
−1600
−1325
0.0
Min
35
−1145
−1945
−1165
−1165
V
EE
−1945
−1525
−1425
25°C
Typ
45
−1020
−1725
Max
55
−895
−1600
V
CC
−880
−1600
−1600
−1325
0.0
Min
35
−1145
−1945
−1165
−1165
V
EE
−1945
−1525
−1425
85°C
Typ
48
−1020
−1725
Max
58
−895
−1600
V
CC
−880
mV
−1600
−1600
−1325
0.0
mV
V
Unit
mA
mV
mV
mV
V
IL
V
BB
V
IHCMR
V
EE
+1.2
V
EE
+1.2
V
EE
+1.2
I
IH
I
IL
150
0.5
−150
−150
150
0.5
−150
−150
150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
10. Input and output parameters vary 1:1 with V
CC
.
11. All loading with 50
W
to V
CC
− 2.0 V.
12. Single−Ended input operation is limited to V
EE
from −3.0 V to −5.5 V in NECL mode.
13. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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