NB100EP223
3.3V 1:22 Differential
HSTL/PECL to HSTL Clock
Driver with LVTTL Clock
Select and Output Enable
Description
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MARKING
DIAGRAM*
The NB100EP223 is a low skew 1−to−22 differential clock driver,
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
aligned low skew signals to their destination. The two clock inputs are
differential HSTL or LVPECL and they are selected by the CLK_SEL
pin which is LVTTL. To avoid generation of a runt clock pulse when
the device is enabled/disabled, the Output Enable (OE), which is
LVTTL, is synchronous ensuring the outputs will only be
enabled/disabled when they are already in LOW state (See Figure 7).
The NB100EP223 guarantees low output−to−output skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output pair, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to “reduce power and switching noise as much as
possible.” Any unused single line of a differential pair should be
terminated the same as the used line to maintain balanced loads on the
differential driver outputs. The output structure uses an open emitter
architecture and will be terminated with 50
W
to ground instead of a
standard HSTL configuration (See Figure 6). The wide VIHCMR
specification allows both pair of CLOCK inputs to accept LVDS
levels.
Features
LQFP−64
FA SUFFIX
CASE 848G
A
WL
YY
WW
G
NB100
EP223
AWLYYWWG
64
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
•
100 ps Typical Device−to−Device Skew
•
25 ps Typical Within Device Skew
•
HSTL Compatible Outputs Drive 50
W
to Ground With No
•
•
•
•
•
•
•
Offset Voltage
Maximum Frequency >500 MHz
1 ns Typical Propagation Delay
LVPECL and HSTL Mode Operating Range: V
CC
= 3 V to 3.6 V
with GND = 0 V, V
CCO
= 1.6 V to 2.0 V
Q Output will Default Low with Inputs Open
Thermally Enhanced 64−Lead LQFP
CLOCK Inputs are LVDS−Compatible; Requires External 100
W
LVDS Termination Resistor
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
−
Rev. 7
1
Publication Order Number:
NB100EP223/D
NB100EP223
V
CCO
V
CCO
33
32
31
30
29
28
27
26
25
Q10
Q10
Q12
Q12
Q13
35
Q13
34
Q11
39
V
CC0
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
V
CC0
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
47
46
45
44
43
42
41
40
Q11
38
Q7
Q7
Q8
Q8
Q9
Q9
37
36
V
CC0
Q14
Q14
Q15
Q15
Q16
Q16
Q17
Q17
Q18
Q18
Q19
Q19
Q20
Q20
V
CC0
NB100EP223
24
23
22
21
20
19
18
17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
NC
V
CC0
V
CC
NC
HSTL_CLK
HSTL_CLK
CLK_SEL
LVPECL_CLK
All V
CC
, V
CCO
, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (V
CC
0
V
CCO
).
The thermally conductive exposed pad on package bottom (see package case drawing) is electrically connected to GND internally.
Figure 1. 64−Lead LQFP Pinout
(Top View)
Table 1. PIN DESCRIPTION
PIN
HSTL_CLK*, HSTL_CLK**
FUNCTION
LVPECL_CLK
Table 2. FUNCTION TABLE
OE*
L
L
H
H
CLK_SEL
L
H
L
H
Q0−Q21
L
L
HSTL_CLK
LVPECL_CLK
Q0−Q21
H
H
HSTL_CLK
LVPECL_CLK
HSTL, LVPECL or LVDS Differential Inputs
LVPECL_CLK*, LVPECL_CLK** LVPECL Differential Inputs
CLK_SEL**
LVCMOS/LVTTL Input CLK Select
OE**
LVCMOS/LVTTL Output Enable
Q0−Q21, Q0−Q21
HSTL Differential Outputs
V
CC
V
CCO
GND***
Positive Supply_Core (3.0 V
−
3.6 V)
* The OE (Output Enable) signal is synchronized with the
Positive Supply_HSTL Outputs(1.6V−2.0V) rising edge of the HSTL_CLK and LVPECL_CLK signal.
Ground
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the package is electrically connected to GND internally.
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2
V
CC0
GND
Q21
Q21
OE
NB100EP223
CLK_SEL
HSTL_CLK
HSTL_CLK
LVPECL_CLK
V
CC
GND
LVPECL_CLK
OE
D
0
22
22
1
Q
V
CCO
Q0−Q21 (HSTL)
Q0−Q21 (HSTL)
Figure 2. Logic Diagram
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
LQFP−64
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Oxygen Index: 28 to 34
Level 2
Value
75 kW
37.5 kW
> 2 kV
> 150 V
> 2 kV
Pb−Free Pkg
Level 3
Moisture Sensitivity (Note 1)
UL 94 V−0 @ 0.125 in
693
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
CCO
V
I
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Core Power Supply
HSTL Output Power Supply
PECL Mode Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(See Application Information)
Thermal Resistance (Junction−to−Case)
(See Application Information)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
0 lfpm
500 lfpm
64 LQFP
64 LQFP
64 LQFP
64 LQFP
Condition 1
GND = 0 V
GND = 0 V
GND = 0 V
Continuous
Surge
Condition 2
V
CCO
= 1.8 V
V
CC
= 3.3 V
V
I
≤
V
CC
Rating
4
4
4
50
100
0 to +85
−65
to +150
35.6
30
3.2
6.4
265
265
Unit
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
NB100EP223
Table 5. LVPECL DC CHARACTERISTICS
V
CC
= 3.3 V; V
CCO
= 1.8 V; GND = 0 V
0°C
Symbol
I
CC
V
IH
V
IL
V
IHCMR
Characteristic
Power Supply Current
V
CC
Min
82
2135
1490
Typ
100
Max
130
2420
1675
Min
82
2135
1490
25°C
Typ
100
Max
130
2420
1675
Min
82
2135
1490
85°C
Typ
100
Max
130
2420
1675
Unit
mA
mV
mV
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Input HIGH Voltage Common Mode
Range (Differential) (Note 2) (Figure 4)
LVPECL_CLK/LVPECL_CLK
HSTL_CLK/HSTL_CLK
Input HIGH Current
Input LOW Current
CLK
CLK
1.2
0.3
3.3
1.6
150
1.2
0.3
3.3
1.6
150
1.2
0.3
3.3
1.6
150
V
V
mA
mA
I
IH
I
IL
0.5
−150
0.5
−150
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. V
IHCMR
min varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Table 6. LVTTL/LVCMOS DC CHARACTERISTICS
V
CC
= 3.3 V; V
CCO
= 1.8 V; GND = 0 V
0°C
Symbol
V
IH
V
IL
I
IH
I
IL
Characteristic
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
−150
−300
Min
2.0
0.8
150
300
−150
−300
Typ
Max
Min
2.0
0.8
150
300
−150
−300
25°C
Typ
Max
Min
2.0
0.8
150
300
85°C
Typ
Max
Unit
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 7. HSTL DC CHARACTERISTICS
V
CC
= 3.3 V; V
CCO
= 1.6−2.0 V; GND = 0 V
0°C
Symbol
V
OH
V
OL
V
IH
V
IL
V
X
I
IH
I
IL
Characteristic
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Differential)
HSTL_CLK/HSTL_CLK
Input LOW Voltage (Differential)
HSTL_CLK/HSTL_CLK
Differential Cross Point Voltage
Input HIGH Current
Input LOW Current
Min
1000
0
V
X
+100
−300
680
−150
−300
Typ
Max
1200
400
1600
V
X
−100
900
150
300
Min
1000
0
V
X
+100
−300
680
−150
−300
25°C
Typ
Max
1200
400
1600
V
X
−100
900
150
300
Min
1000
0
V
X
+100
−300
680
−150
−300
85°C
Typ
Max
1200
400
1600
V
X
−100
900
150
300
Unit
mV
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. All outputs loaded with 50
W
to GND (See Figure 6).
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NB100EP223
Table 8. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V; V
CCO
= 1.6 V to 2.0 V; GND = 0 V (Note 4)
0°C
Symbol
V
Opp
t
PLH
t
PHL
t
skew
t
JITTER
V
PP
t
S
t
H
t
r
/t
f
Characteristic
Differential Output Voltage
(Figure 3)
f
out
< 500 MHz
Min
600
700
800
Typ
750
900
900
25
100
0.5
150
1.0
0.5
300
450
700
800
1000
1100
50
250
2
1200
150
1.0
0.5
275
450
700
Max
Min
600
750
850
25°C
Typ
750
900
950
30
200
0.5
800
1100
1200
65
450
2
1200
150
1.0
0.5
350
500
750
Max
Min
600
800
850
85°C
Typ
700
1000
1050
50
250
0.5
800
1300
1350
115
450
2
1200
Max
Unit
mV
Propagation Delay (Differential)
LVPECL_CLK to Q
HSTL_CLK to Q
Within−Device Skew (Note 5)
Device−to−Device Skew (Note 6)
Random Clock Jitter (Figure 3) (RMS)
Input Swing (Differential Mode)
(Note 8) (Figure 4)
LVPECL, HSTL
OE Set Up Time (Note 7)
OE Hold Time
Output Rise/Fall Time (20%−80%)
ps
ps
ps
ps
ps
mV
ns
ns
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50
W
to ground
(See Figure 6).
5. Skew is measured between outputs under identical transitions and conditions on any one device.
6. Device−to−Device skew for identical transitions at identical V
CC
levels.
7. OE Set Up Time is defined with respect to the rising edge of the clock. OE High−to−Low transition ensures outputs remain disabled during
the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock (See Figure 7).
8. V
PP
is the differential input voltage swing required to maintain AC characteristics including t
PD
and device−to−device skew.
900
OUTPUT AMPLITUDE (mV)
800
700
600
500
400
300
200
0.5
0.6
RMS JITTER (ps)
0.7
0.8
0.9
1.0
Q AMP (mV)
10
9.0
8.0
6.0
5.0
4.0
3.0
2.0
1.0
0
RMS JITTER (ps)
7.0
FREQUENCY (GHz)
Figure 3. Output Frequency (F
OUT
) versus Output Voltage (V
OPP
) and Random Clock Jitter (t
JITTER
)
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