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NB6N14S

产品描述6N SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16
产品类别半导体    逻辑   
文件大小279KB,共11页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
下载文档 详细参数 选型对比 全文预览

NB6N14S概述

6N SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16

6N 系列, 低偏移时钟驱动器, 4 实输出(S), 0 反向输出(S), QCC16

NB6N14S规格参数

参数名称属性值
功能数量1
端子数量16
最大工作温度85 Cel
最小工作温度-40 Cel
最大供电/工作电压3.6 V
最小供电/工作电压3 V
额定供电电压3.3 V
加工封装描述3 × 3 MM, 铅 FREE, QFN-16
无铅Yes
欧盟RoHS规范Yes
中国RoHS规范Yes
状态ACTIVE
包装形状SQUARE
包装尺寸芯片 CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
表面贴装Yes
端子形式NO 铅
端子间距0.5000 mm
端子涂层MATTE 锡
端子位置
包装材料UNSPECIFIED
温度等级INDUSTRIAL
系列6N
输入条件微分
逻辑IC类型低偏移时钟驱动器
反相输出数0.0
真实输出数4
传播延迟TPD0.6000 ns
最大同边弯曲0.0200 ns

文档预览

下载PDF文档
NB6N14S
3.3 V 1:4 AnyLevelt
Differential Input to LVDS
Fanout Buffer/Translator
The NB6N14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevelt differential input signals: LVPECL, CML or
LVDS. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N14S has a wide input common mode range from
GND + 50 mV to V
CC
50 mV. Combined with the 50
W
internal
termination resistors at the inputs, the NB6N14S is ideal for
translating a variety of differential or single−ended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N14S is offered in a small 3 mm x 3 mm 16−QFN
package. Application notes, models, and support documentation are
available at
www.onsemi.com.
The NB6N14S is a member of the ECLinPS MAXt family of high
performance products.
Features
http://onsemi.com
MARKING
DIAGRAM*
16
1
1
QFN−16
MN SUFFIX
CASE 485G
NB6N
14S
ALYW
G
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum RMS Clock Jitter
Typically 10 ps Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
V
REF_AC
Reference Output
TIA/EIA
644 Compliant
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
These are Pb−Free Devices
Q0
Q0
Q1
IN
W
VT 50
50
W
/IN
+
R
PU
EN
(LVTTL/CMOS)
D
Q
Q3
Q3
Q1
Q2
Q2
VOLTAGE (130 mV/div)
V
REF_AC
Figure 1. Logic Diagram
Device DDJ = 10 ps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2
23−1
(V
INPP
= 400 mV; Input Signal DDJ = 14 ps)
TIME (58 ps/div)
©
Semiconductor Components Industries, LLC, 2013
September, 2013
Rev. 8
1
Publication Order Number:
NB6N14S/D

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NB6N14S NB6N14SMNGEVB NB6N14SMNG
描述 6N SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 BOARD EVAL FOR NB6N14SMNG
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端子数量 16 - 16
表面贴装 Yes - YES
端子形式 NO 铅 - NO LEAD
端子位置 - QUAD
温度等级 INDUSTRIAL - INDUSTRIAL
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