NB6L11M
2.5V / 3.3V 1:2 Differential
CML Fanout Buffer
Multi−Level Inputs w/ Internal Termination
Description
http://onsemi.com
MARKING
DIAGRAM*
16
1
QFN−16
MN SUFFIX
CASE 485G
NB6L
11M
ALYWG
G
The NB6L11M is a differential 1:2 CML fanout buffer. The
differential inputs incorporate internal 50
W
termination resistors that
are accessed through the V
T
pins and will accept LVPECL, LVCMOS,
LVTTL, CML, or LVDS logic levels.
The V
REFAC
pin is an internally generated voltage supply available
to this device only. V
REFAC
is used as a reference voltage for
single−ended PECL or NECL inputs. For all single−ended input
conditions, the unused complementary differential input is connected
to V
REFAC
as a switching reference voltage. V
REFAC
may also rebias
capacitor−coupled inputs. When used, decouple V
REFAC
with a
0.01
mF
capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
REFAC
output should be left open.
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L11M is a member of the ECLinPS MAXt family of
high performance clock products.
Features
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 4 GHz, Typical
225 ps Typical Propagation Delay
70 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
Differential CML Outputs, 380 mV peak−to−peak, typical
LVPECL Operating Range: V
CC
= 2.375 V to 3.63 V with V
EE
= 0 V
NECL Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.63 V
Internal Input Termination Resistors, 50
W
VREFAC Reference Output
Functionally Compatible with Existing 2.5 V / 3.3V LVEL, LVEP,
EP, and SG Devices
•
−40°C to +85°C Ambient Operating Temperature
•
These are Pb−Free Devices
Q0
VTD
D
D
VTD
V
REFAC
Q0
Q1
Q1
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
1
March, 2007 − Rev. 1
Publication Order Number:
NB6L11M/D
NB6L11M
V
CC
16
VTD
D
D
VTD
V
EE
V
EE
15
14
V
CC
13
Q0
Q0
Q1
Q1
Exposed Pad (EP)
1
2
NB6L11M
3
4
12
11
10
9
5
6
7
8
V
CC
V
CC
V
REFAC
V
EE
Figure 2. Pin Configuration
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
Name
VTD
D
I/O
−
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
−
−
Internal 50
W
Termination Pin for D input.
Noninverted Differential Input. Note 1. Internal 50
W
Resistor to Termination Pin, VTD.
Description
3
D
Inverted Differential Input. Note 1. Internal 50
W
Resistor to Termination Pin, VTD.
4
5
6
7
8
9
10
11
12
13
14
15
16
−
VTD
V
CC
V
REFAC
V
EE
V
CC
Q1
Q1
Q0
Q0
V
CC
V
EE
V
EE
V
CC
EP
Internal 50
W
Termination Pin for D input.
Positive Supply Voltage
Output Reference Voltage for direct or capacitor coupled inputs
−
−
CML Output
CML Output
CML Output
CML Output
−
−
−
−
−
Negative Supply Voltage
Positive Supply Voltage
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Noninverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Noninverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Positive Supply Voltage
Negative Supply Voltage
Negative Supply Voltage
Positive Supply Voltage
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is not electrically connected to the die, but is recommended to be electrically
and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and
if no signal is applied on D/D input, then, the device will be susceptible to self−oscillation.
2. All V
CC
and V
EE
pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2
NB6L11M
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
16−QFN
Oxygen Index: 28 to 34
Value
> 2 kV
> 200V
Level 1
UL 94 V−0 @ 0.125 in
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
IO
V
INPP
I
IN
I
OUT
I
VREFAC
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input/Output Voltage
Negative Input/Output Voltage
Differential Input Voltage |D − D|
Input Current Through R
T
(50
W
Resistor)
Output Current (CML Output)
VREFAC Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder Pb−Free
0 lfmp
500 lfmp
(Note 3)
QFN−16
QFN−16
QFN−16
16 QFN
Static
Surge
Continuous
Surge
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
−0.5
v
V
Io
v
V
CC
+ 0.5
+0.5
v
V
Io
v
V
EE
− 0.5
Condition 2
Rating
4.0
−4.0
4.0
−4.0
V
CC
− V
EE
45
80
25
50
$0.5
−40 to +85
−65 to +150
42
35
4
265
Unit
V
V
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C/W
_C/W
_C/W
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
3
NB6L11M
Table 4. DC CHARACTERISTICS, Multi−Level Inputs
V
CC
= 2.375 V to 3.63 V, V
EE
= 0 V, or V
CC
= 0 V, V
EE
= −2.375 V to
−3.63 V, T
A
= −40°C to +85°C
Symbol
POWER SUPPLY CURRENT
I
CC
Power Supply Current (Inputs and Outputs Open)
45
60
75
mA
Characteristic
Min
Typ
Max
Unit
CML OUTPUTS
(Notes 4 and 5)
V
OH
Output HIGH Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
V
OL
Output LOW Voltage
V
CC
= 3.3V
V
CC
= 2.5V
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(see Figures 4 and 5) (Note 6)
V
th
V
IH
V
IL
V
ISE
VREFAC
V
REFAC
Output Reference Voltage
V
CC
– 1525
V
CC
– 1425
V
CC
– 1325
mV
Input Threshold Reference Voltage Range (Note 7)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Single−ended Input Voltage Amplitude (V
IH
− V
IL
)
1125
V
th
+ 75
V
EE
150
V
CC
− 75
V
CC
V
th
− 75
2800
mV
mV
mV
mV
V
CC
− 40
3260
2460
V
CC
− 500
2800
2000
V
CC
− 10
3290
2490
V
CC
− 400
2900
2100
V
CC
3300
2500
V
CC
− 300
3000
2200
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(see Figures 6, 7 and 8) (Note 8)
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
− V
ILD
)
Input Common Mode Range (Differential Configuration) (Note9)
Input HIGH Current D / D, (VTD/VTD Open)
Input LOW Current D / D, (VTD/VTD Open)
V
EE
+ 1200
V
EE
V
EE
+ 100
V
EE
+ 1150
−10
−50
V
CC
V
CC
− 100
V
CC
− V
EE
V
CC
− 50
50
10
mV
mV
mV
mV
uA
uA
TERMINATION RESISTORS
R
TIN
R
TOUT
Internal Input Termination Resistor
Internal Output Termination Resistor
40
40
50
50
60
60
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. CML outputs loaded with 50
W
to V
CC
for proper operation.
5. Input and output parameters vary 1:1 with V
CC
.
6. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
9. V
CMR
min varies 1:1 with V
EE
, V
CMR
maximum varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
http://onsemi.com
4
NB6L11M
Table 5. AC CHARACTERISTICS
V
CC
= 2.375 V to 3.63 V, V
EE
= 0 V, or V
CC
= 0 V, V
EE
= −2.375 V to −3.63 V, T
A
= −40°C to
+85°C; (Note 10)
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (@ V
INPP(MIN)
(Note 15) (See Figure 9)
Propagation Delay
Duty Cycle Skew (Note 11)
Within Device Skew
Device to Device Skew (Note 12)
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
RMS Random Clock Jitter (Note 13)
Peak−to−Peak Data Dependent Jitter
(Note 14)
V
INPP
t
r
t
f
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
Output Rise/Fall Times @ 0.5 GHz
(20% − 80%)
Q, Q
f
in
≤
4.0GHz
f
in
≤
4GHz
f
in
≤
4Gb/s
150
70
40
f
in
≤
3.0GHz
f
in
≤
3.5 GHz
f
in
≤
4.0 GHz
D to Q
Min
230
190
150
175
Typ
380
320
270
225
5.0
3.0
50
0.2
40
2800
120
mV
ps
325
15
15
80
60
0.5
Max
Unit
mV
t
PD
t
SKEW
ps
ps
t
DC
t
JITTER
%
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All loading with an external R
L
= 50
W
to V
CC
. Input edge rates 40 ps
(20% − 80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5GHz.
12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23.
15. Input and output voltage swing is a single−ended measurement operating in differential mode.
http://onsemi.com
5
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
