NB4N840M
3.3V 3.2Gb/s Dual
Differential Clock/Data 2 x 2
Crosspoint Switch with
CML Output and Internal
Termination
Description
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MARKING
DIAGRAM
1
32
1
The NB4N840M is a high−bandwidth fully differential dual
2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
applications such as SDH/SONET, DWDM, Gigabit Ethernet and
high speed switching. Fully differential design techniques are used to
minimize jitter accumulation, crosstalk, and signal skew, which make
this device ideal for loop−through and protection channel switching
applications.
Internally terminated differential CML inputs accept AC−coupled
LVPECL (Positive ECL) or direct coupled CML signals. By providing
internal 50
W
input and output termination resistor, the need for
external components is eliminated and interface reflections are
minimized. Differential 16 mA CML outputs provide matching
internal 50
W
terminations, and 400 mV output swings when
externally terminated, 50
W
to V
CC
.
Single−ended LVCMOS/LVTTL SEL inputs control the routing of
the signals through the crosspoint switch which makes this device
configurable as 1:2 fan−out, repeater or 2 x 2 crosspoint switch. The
device is housed in a low profile 5 x 5 mm 32−pin QFN package.
Features
QFN32
MN SUFFIX
CASE 488AM
A
WL
YY
WW
G
NB4N
840M
ALYWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
DA0
DA0
CML
0
CML
1
QA0
QA0
ENA0
SELA0
QA1
CML
QA1
ENA1
SELA1
0
DA1
DA1
CML
1
•
•
•
•
•
•
•
•
•
•
•
•
Plug−in compatible to the MAX3840 and SY55859L
Maximum Input Clock Frequency 2.7 GHz
Maximum Input Data Frequency 3.2 Gb/s
225 ps Typical Propagation Delay
80 ps Typical Rise and Fall Times
7 ps Channel to Channel Skew
430 mW Power Consumption
< 0.5 ps RMS Jitter
7 ps Peak−to−Peak Data Dependent Jitter
Power Saving Feature with Disabled Outputs
Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
CML Output Level (400 mV Peak−to−Peak Output), Differential
Output
•
These are Pb−Free Devices
DB0
DB0
CML
0
1
QB0
CML
QB0
ENB0
SELB0
0
DB1
DB1
CML
1
CML
QB1
QB1
ENB1
SELB1
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 5
Publication Order Number:
NB4N840M/D
NB4N840M
Table 1. TRUTH TABLE
SELA0/SELB0
L
L
H
H
X
SELA1/SELB1
L
H
L
H
X
ENA0/ENA1
H
H
H
H
L
ENB0/ENB1
H
H
H
H
L
QA0/QB0
DA0/DB0
DA0/DB0
DA1/DB1
DA1/DB1
Disable/Power Down
QA1/QB1
DA0/DB0
DA1/DB1
DA0/DB0
DA1/DB1
Disable/Power Down
Function
1:2 Fanout
Quad Repeater
Crosspoint Switch
1:2 Fanout
No output (@ V
CC
)
SELA0
32
ENB1
DB1
DB1
ENB0
SELB0
DB0
DB0
SELB1
1
2
3
4
31
30
29
28
27
26
25
24
23
22
21
GND
V
CC
QA0
QA0
V
CC
QA1
QA1
V
CC
NB4N840M
5
6
7
8
9
GND
10
V
CC
11
QB0
12
QB0
13
V
CC
14
QB1
15
QB1
16
V
CC
20
19
18
17
Figure 2. Pin Configuration (Top View)
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2
SELA1
ENA1
ENA0
DA1
DA1
DA0
DA0
NB4N840M
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9,24
10, 13, 16,
17, 20, 23
11
12
14
15
18
19
21
22
25
26
27
28
29
30
31
32
−
Name
ENB1
DB1
DB1
ENB0
SELB0
DB0
DB0
SELB1
GND
V
CC
QB0
QB0
QB1
QB1
QA1
QA1
QA0
QA0
SELA1
DA0
DA0
SELA0
ENA0
DA1
DA1
ENA1
EP
I/O
LVTTL
CML Input
CML Input
LVTTL
LVTTL
CML Input
CML Input
LVTTL
−
−
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
LVTTL
CML Input
CML Input
LVTTL
LVTTL
CML Input
CML Input
LVTTL
GND
Description
Channel B1 Output Enable. LVTTL low input powers down B1 output stage.
Channel B1 Positive Signal Input
Channel B1 Negative Signal Input
Channel B0 Output Enable. LVTTL low input powers down B0 output stage.
Channel B0 Output Select. See Table 1.
Channel B0 Positive Signal Input
Channel B0 Negative Signal Input
Channel B1 Output Select. See Table 1.
Supply Ground. All GND pins must be externally connected to power supply to guarantee
proper operation.
Positive Supply. All V
CC
pins must be externally connected to power supply to guarantee
proper operation.
Channel B0 Negative Output.
Channel B0 Positive Output.
Channel B1 Negative Output.
Channel B1 Positive Output.
Channel A1 Negative Output.
Channel A1 Positive Output.
Channel A0 Negative Output.
Channel A0 Positive Output.
Channel A1 Output Select, LVTTL Input. See Table 1.
Channel A0 Positive Signal Input.
Channel A0 Negative Signal Input.
Channel A0 Output Select, LVTTL Input. See Table 1.
Channel A0 Output Enable. LVTTL low input powers down A0 output stage.
Channel A1 Positive Signal Input.
Channel A1 Negative Signal Input.
Channel A1 Output Enable. LVTTL low input powers down A1 output stage.
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing)
must be attached to a heat−sinking conduit. The exposed pad must be soldered to the
circuit board GND for proper electrical and thermal operation.
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NB4N840M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Human Body Model
Machine Model
QFN−32
Oxygen Index: 28 to 34
Value
> 2000 V
> 110 V
Level 1
UL 94 V−0 @ 0.125 in
380
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
I
V
INPP
I
IN
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Input
Differential Input Voltage
|D − D|
Static
Surge
Continuous
Surge
QFN−32
Condition 1
GND = 0 V
GND = 0 V
GND = V
I
= V
CC
Condition 2
Rating
3.8
3.8
3.8
45
80
25
80
−40 to +85
−65 to +150
0 lfpm
500 lfpm
2S2P (Note 3)
<3 sec @ 260 C
QFN−32
QFN−32
QFN−32
31
27
12
260
Unit
V
V
V
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Input Current Through Internal 50
W
Resistor
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 2)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB4N840M
Table 5. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS
V
CC
= 3.0 V to 3.6 V, T
A
= −40°C to +85°C
Symbol
I
CC
Vout
diff
V
CMR
(Note 6)
V
ID
Characteristic
Power Supply Current (All outputs enabled)
CML Differential Output Swing (Note 4, Figures 5 and 12)
CML Output Common Mode Voltage (Loaded 50
W
to V
CC
)
CML Single−Ended Input Voltage Range
Differential Input Voltage (V
IHD
− V
ILD
)
V
CC
− 800
300
640
Min
Typ
130
800
V
CC
− 200
V
CC
+ 400
1600
Max
170
1000
Unit
mA
mV
mV
mV
mV
LVTTL CONTROL INPUT PINS
V
IH
V
IL
I
IH
I
IL
R
TIN
R
TOUT
Input HIGH Voltage (LVTTL Inputs)
Input LOW Voltage (LVTTL Inputs)
Input HIGH Current (LVTTL Inputs)
Input LOW Current (LVTTL Inputs)
CML Single−Ended Input Resistance
Differential Output Resistance
−10
−10
42.5
85
50
100
2000
800
10
10
57.5
115
mV
mV
mA
mA
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. CML outputs require 50
W
receiver termination resistors to V
CC
for proper operation (Figure 10).
5. Input and output parameters vary 1:1 with V
CC
.
6. V
CMR
min varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
.
Table 6. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, V
EE
= 0 V (Note 7, Figure 9)
−40°C
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (@ V
INPPmin
)
(See Figure 3)
Maximum Operating Data Rate
Propagation Delay to Output Differential
D/D to Q/Q
Duty Cycle Skew (Note 8)
Within−Device Skew (Figure 4)
Device−to−Device Skew (Note 12)
RMS Random Clock Jitter (Note 10) f
in
v
3.2 GHz
Peak−to−Peak Data Dependent Jitter f
in
= 2.5 Gb/s
(Note 11)
f
in
= 3.2 Gb/s
Crosstalk−Induced RMS Jitter (Note 13)
V
INPP
t
r
t
f
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 9)
Output Rise/Fall Times @ 0.5 GHz
(20% − 80%)
Q, Q
150
80
140
225
5
5
20
0.15
7
7
340
25
25
85
0.5
20
20
0.5
800
135
150
80
140
225
5
5
20
0.15
7
7
340
25
25
85
0.5
20
20
0.5
800
135
150
80
140
225
5
5
20
0.15
7
7
340
25
25
85
0.5
20
20
0.5
800
135
ps
f
in
≤
2 GHz
f
in
≤
3 GHz
f
in
≤
3.5 GHz
Min
280
235
170
3.2
Typ
365
310
220
Max
Min
280
235
170
3.2
25°C
Typ
365
310
220
Max
Min
280
235
170
3.2
85°C
Typ
365
310
220
Max
Unit
mV
f
DATA
t
PLH
,
t
PHL
t
SKEW
Gb/s
ps
t
JITTER
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All loading with an external R
L
= 50
W
to V
CC
. Input edge rates 40 ps
(20% − 80%).
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
9. V
INPP
(MAX) cannot exceed 800 mV. Input voltage swing is a single−ended measurement operating in differential mode.
10. Additive RMS jitter using 50% duty cycle clock input signal.
11. Additive peak−to−peak data dependent jitter using input data pattern with PRBS 2
23
−1 and K28.5, V
INPP
= 400 mV.
12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13. Data taken on the same device under identical condition.
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