NB4N441
3.3V Serial Input
MultiProtocol PLL Clock
Synthesizer, Differential
LVPECL Output
Description
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MARKING
DIAGRAM*
24
QFN−24
MN SUFFIX
CASE 485L
1
NB4N
441
ALYWG
G
The NB4N441 is a precision clock synthesizer which generates a
differential LVPECL clock output frequency from 12.5 MHz to
425 MHz. A Serial Peripheral Interface (SPI) is used to configure the
device to produce one of sixteen popular standard protocol output
frequencies from a single 27 MHz crystal reference. The NB4N441
also has the added feature of allowing application specific output
frequencies from 12.5 MHz to 425 MHz using crystals within the
range of 10 MHz to 28 MHz.
Features
•
Performs Precision Clock Generation and Synthesis from a Single
•
•
•
•
•
•
•
•
•
27 MHz Crystal Reference
Serial Load Capability for Proprietary Frequencies
Flexible Input Allows for External Clock Reference
Exceeds Bellcore and ITU Jitter Generation Specification
PLL Lock Detect Output
Output Enable
Fully Integrated Phase−Lock−Loop with Internal Loop Filter
Operating Range: V
CC
= 3.135 V to 3.465 V
Small Footprint 24 Pin QFN
These are Pb−Free Devices*
LOCKED
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
27 MHz
XTAL
OSC
B
R
FB
Feedback
Divider
OUTDIV
B2,
4, 8,
16, 32
CLKOUT
CLKOUT
OE
V
CC
−
2 V
SDATA
SCLOCK
SLOAD
Frequency Control Logic
Serial Load
Figure 1. Simplified Block Diagram
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2011
April, 2011
−
Rev. 2
1
Publication Order Number:
NB4N441/D
NB4N441
V
CC
LOCKED
Input
Prescaler
XTAL
OSC
PB
R
FB
Feedback
Divider (MB)
PFD
VCC_PLL
Loop
Filter
CLK/XTAL1
XTAL2
VCO
OUTDIV (NB)
B2,
4, 8,
16, 32
OE
CLKOUT
CLKOUT
SDATA
SCLOCK
SLOAD
P[4:0] M[9:0] N[3:0]
Frequency Control Logic
Serial Load
GND
Figure 2. Block Diagram
LOCKED
CLKOUT
CLKOUT
24
GND
NC
VCC_PLL
NC
NC
GND
1
2
3
4
5
6
7
XTAL2
23
22
21
20
GND
V
CC
OE
Exposed Pad
(EP)
19
18
17
16
15
14
13
GND
SCLOCK
SDATA
SLOAD
NC
V
CC
8
CLK/XTAL1
9
GND
10
NC
11
V
CC
12
V
CC
Figure 3. QFN−24 Lead Pinout
(Top View)
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2
NB4N441
Table 1. PIN DESCRIPTION
Pin
11, 12, 13, 24
3
1, 6, 9, 18, 19
20
Name
V
CC
VCC_PLL
GND
LOCKED
I/O
Power Supply
PLL Power Supply
Ground
LVTTL Lock Output
Positive supply voltage.
Positive supply voltage for the PLL.
Ground.
When Low, this output provides indication that the PLL is
locked and the device is in proper operating mode. When
High, the PLL is out of lock.
No Connect.
LVTTL/LVCMOS Single Ended
Clock or XTAL Inputs
LVTTL / LVCMOS,
Serial Load Input
LVTTL / LVCMOS
Serial Data Input
LVTTL / LVCMOS
Serial Clock Input
LVTTL Input
The crystal is connected between the XTAL1 and XTAL2 pin.
If driving single−ended, use XTAL1 and leave XTAL2
floating.
Serial Load.
Serial Data Input.
Serial Clock Input.
Synchronous Output Enable. When OE is HIGH or left
OPEN, the outputs are enabled. When OE is LOW, the
outputs are disabled.
Differential LVPECL Clock Outputs, Typically terminated with
50
W
resistor to VCC – 2.0 V.
The Exposed Pad on the 24 pin QFN package bottom is
thermally connected to the die for improved heat transfer out
of package. The pad is not electrically connected to the die,
but is recommended to be electrically connected to GND on
the PC board.
Description
2, 4, 5, 10, 14
8
7
15
16
17
21
NC
CLK / XTAL1,
XTAL2
SLOAD**
SDATA**
SCLOCK**
OE*
22, 23
CLKOUT
CLKOUT
EP
LVPECL Output
*Pins will default HIGH when left Open
**Pins will default LOW when left Open
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NB4N441
Table 2. STANDARD PROTOCOL / OUTPUT FREQUENCY SELECT TABLE WITH 27 MHz CRYSTAL REFERENCE
#
0
0
0
1
2
3
3
4
4
4
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Protocol
OC−3 /STM−1
OC−12 / STM−4
OC−48 / STM−16
ETR
OC−1
Fast Ethernet
ESCON
FDDI
Infiniband
Gigabit Ethernet
PCIe
1/8 Fibre Channel
1/4 Fibre Channel
1/2 Fibre Channel
Fibre Channel
General
D1 Video
SONET Reference
2x Fibre Channel
4x Fibre Channel
XAUI
Serial ATA
HDTV
HDTV
CLKOUT (MHz)
155.52
155.52
155.52
32
51.84
50
50
125
125
125
125
13.28125
26.5625
53.125
106.25
150
69
19.44
212.5
425
156.25
100
74.25
148.50
Input Prescaler
Divider P[4:0]
11001
11001
11001
11011
11001
11011
11011
11011
11011
11011
11011
11011
11011
11011
11011
11011
11011
11001
11011
11011
11011
11011
11011
11011
PLL FB Divider
M[9:0]
1001000000
1001000000
1001000000
1000000000
1100000000
1100100000
1100100000
0111110100
0111110100
0111110100
0111110100
0110101001
1101010010
1101010010
1101010010
1001011000
1000101000
1001000000
1101010010
1101010010
1001110001
1100100000
1001010010
1001010010
Output Frequency Divider
OUTDIV N[2:0]
010
010
010
100
100
100
100
010
010
010
010
101
101
100
011
010
011
101
010
001
010
011
011
010
Table 3. N−DIVIDER TABLE
N2
0
0
0
0
1
1
1
1
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
N Divider
na
B2
B4
B8
B16
B32
na
na
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4
NB4N441
Table 4. ATTRIBUTES
Characteristics
Internal Input Pullup Resistor
Internal Input Pulldown Resistor
ESD Protection
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
37.5kW
75kW
> 1000 V
> 150 V
Level 1
UL 94 V−0 @ 0.125 in
2102
Table 5. MAXIMUM RATINGS
(Note 2)
Symbol
V
CC
V
I
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Positive Power Supply
Input Voltage
LVPECL Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder
0 lfpm
500 lfpm
2S2P (Note 3)
< 3 sec @ 260°C
QFN−24
QFN−24
QFN−24
265
Parameter
Condition 1
GND = 0 V
GND = 0 V
Continuous Surge
QFN−24
GND = V
I
= V
CC
Condition 2
Rating
3.6
3.6
50
100
−40
to +85
−65
to +150
Unit
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum Ratings are those values beyond which device damage may occur.
3. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power).
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