NB4L52
2.5 V/3.3 V/5.0 V Differential
Data/Clock D Flip-Flop
with Reset
Multi−Level Inputs to LVPECL Translator
w/ Internal Termination
The NB4L52 is a differential Data and Clock D flip−flop with a
differential asynchronous Reset. The differential inputs incorporate
internal 50
W
termination resistors and will accept PECL, LVPECL,
LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock
transitions from Low to High, Data will be transferred to the
differential LVPECL outputs. The differential Clock inputs allow the
NB4L52 to also be used as a negative edge triggered device. The
device is housed in a small 3x3 mm 16 pin QFN package.
Features
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MARKING DIAGRAM*
16
1
1
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
NB4L
52
ALYWG
G
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 4 GHz Typical
330 ps Typical Propagation Delay
145 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical
Operating Range: V
CC
= 2.375 V to 5.5 V with V
EE
= 0 V
Internal Input Termination Resistors, 50
W
Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL,
LVEP, EP, and SG Devices
•
−40°C
to +85°C Ambient Operating Temperature
•
These are Pb−Free Devices
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
D
D
VTD
VTCLK
CLK
CLK
VTCLK
Clock
Reset
Q
Data
Q
VTR R
R VTR
Figure 1. Logic Diagram
Table 1. TRUTH TABLE
R
H
L
L
D
x
L
H
CLK
x
Z
Z
Q
L
L
H
Z = LOW to HIGH Transition
x = Don’t Care
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
August, 2009
−
Rev. 3
1
Publication Order Number:
NB4L52/D
NB4L52
V
TR
16
V
TD
D
D
V
TD
1
2
NB4L52
3
4
5
6
7
8
10
9
R
15
R
14
V
TR
13
12
11
V
CC
Q
Q
V
EE
V
TCLK
CLK
CLK V
TCLK
Exposed Pad (EP)
Figure 2. Pinout
(Top View)
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
−
Name
V
TD
D
D
V
TD
V
TCLK
CLK
CLK
V
TCLK
V
EE
Q
Q
V
CC
V
TR
R
R
V
TR
EP
I/O
−
ECL, CML, LVCMOS,
LVDS, LVTTL Input
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
−
ECL, CML, LVCMOS,
LVDS, LVTTL Input
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
−
ECL Output
ECL Output
−
−
LVECL, LVCMOS,
LVTTL Input
LVECL, LVCMOS,
LVTTL Input
−
−
Description
Internal 50
W
Termination Pin. (See Table 4)
Noninverted Differential Input. (Note 1)
Inverted Differential Input. (Note 1)
Internal 50
W
Termination Pin. (See Table 4)
Internal 50
W
Termination Pin. (See Table 4)
Noninverted Differential Input. (Note 1)
Inverted Differential Input. (Note 1)
Internal 50
W
Termination Pin. (See Table 4)
Negative Supply Voltage
Inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
−
2.0 V.
Noninverted Differential Output. Typically terminated with 50
W
resistor to V
CC
−
2.0 V.
Positive Supply Voltage
Internal 50
W
Termination Pin. (See Table 4)
Noninverted Differential Reset Input. (Note 1)
Inverted Differential Reset Input. (Note 1)
Internal 50
W
Termination Pin. (See Table 4)
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The pad is not electrically connected to the die,
but is recommended to be electrically and thermally connected to V
EE
on the PC board.
1. In the differential configuration when the input termination pin (VTD, VTD, VTR, VTR, VTCLK, VTCLK) are connected to a common
termination voltage or left open, and if no signal is applied on D/D,CLK/CLK,R/R input then the device will be susceptible to self−oscillation.
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2
NB4L52
Table 3. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
QFN−16
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Level 1
Value
> 2 kV
> 200 V
> 1 kV
Pb−Free Pkg
Level 1
Moisture Sensitivity (Note 2)
UL 94 V−0 @ 0.125 in
164
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
IO
I
IN
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input/Output
Negative Input/Output
Input Current Through R
T
(50
W
Resistor)
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 LFPM
500 LFPM
2S2P (Note 3)
16 QFN
16 QFN
16 QFN
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Static
Surge
Continuous
Surge
V
I
v
V
CC
V
I
w
V
EE
Condition 2
Rating
6.0
−6.0
6.0
−6.0
45
80
25
50
−40
to +85
−65
to +150
42
35
4.0
265
Unit
V
V
V
V
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB4L52
Table 5. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS
(V
CC
= 2.375 V to 5.5 V, V
EE
= 0 V or V
CC
= 0 V, V
EE
=
−2.375
to
−5.5
V, T
A
=
−40°C
to +85°C)
Symbol
I
EE
V
OH
Characteristic
Power Supply Current (Inputs and Outputs Open)
Output HIGH Voltage (Note 4, 5)
V
CC
= 5.0 V
V
CC
= 3.3 V
V
CC
= 2.5 V
Output LOW Voltage (Note 4, 5)
V
CC
= 5.0V
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
−
1145
3855
2155
1355
V
CC
−
1945
3055
1355
555
Min
Typ
16
V
CC
−
1020
3980
2280
1480
V
CC
−
1770
3230
1530
730
Max
25
V
CC
−
895
4105
2405
1605
V
CC
−
1600
3400
1700
900
Unit
mA
mV
V
OL
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(Figures 4 & 7)
Vth
V
IH
V
IL
V
IHD
V
ILD
V
CMR
V
ID
I
IH
I
IL
R
TIN
Input Threshold Reference Voltage Range (Note 6)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
1050
Vth + 150
V
EE
1200
V
EE
1125
150
(VTx/VTx Open)
(VTx/VTx Open)
−150
−150
40
50
V
CC
−
150
V
CC
Vth
−
150
mV
mV
mV
DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY
(Figures 5, 6 & 8 )
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration) (Note 7)
Differential Input Voltage (V
IHD
−
V
ILD
)
Input HIGH Current
Input LOW Current
D / D, CLK / CLK, R /R
D / D, CLK / CLK, R /R
V
CC
V
CC
−
150
V
CC
– 75
V
CC
150
150
60
mV
mV
mV
mV
mA
mA
W
Internal Input Termination Resistor
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL outputs loaded with 50
W
to V
CC
– 2.0 V for proper operation.
5. Input and output parameters vary 1:1 with V
CC
.
6. V
th
is applied to the complementary input when operating in single−ended mode.
7. V
CMRMIN
varies 1:1 with V
EE
, V
CMRMAX
varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential input
signal.
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NB4L52
Table 6. AC CHARACTERISTICS
V
CC
= 2.375 V to 5.5 V; V
EE
= 0 V or V
CC
= 0 V, V
EE
=
−2.375
to
−5.5
V (Note 8)
−40°C
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (@ V
INPPmin
)
(Note 10) (See Figure 4)
f
in
v
2.0 GHz
f
in
v
3.0 GHz
f
in
v
4.0 GHz
Propagation Delay to
Output Differential
Setup Time
Hold Time
Reset Recovery
Minimum Pulse Width
RMS Random Clock Jitter (Note 9)
R/R
f
in
v
2.0 GHz
f
in
v
3.0 GHz
f
in
v
4.0 GHz
150
80
135
CLK to Q, R to Q
Min
530
490
380
300
100
50
400
250
1
1
1
2800
190
150
80
145
Typ
770
720
580
400
500
Max
Min
530
490
380
300
100
50
400
250
1
1
1
2800
190
150
80
155
25°C
Typ
780
730
580
400
500
Max
Min
530
490
380
300
100
50
400
250
1
1
1
2800
190
85°C
Typ
760
680
530
400
500
Max
Unit
mV
t
PLH
,
t
PHL
t
s
t
h
t
RR
t
PW
t
JITTER
ps
ps
ps
ps
ps
ps
V
INPP
t
r
t
f
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
Output Rise/Fall Times @ 0.5 GHz
(20%
−
80%)
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All loading with an external R
L
= 50
W
to V
CC
– 2.0 V. Input edge
rates 40 ps (20%
−
80%).
9. Additive RMS jitter with 50% duty cycle clock signal.
10. Input and output voltage swing is a single−ended measurement operating in differential mode.
V
OUTPP
, OUTPUT VOLTAGE AMPLITUDE (mV)
(TYPICAL)
800
700
600
500
400
300
200
100
0
0
1
2
3
4
f
in
, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (V
OUTPP
) vs.
Clock Input Frequency at Ambient Temperature (Typical).
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