NB4L339
2.5 V / 3.3 V Differential 2:1
Clock IN to Differential
LVPECL Clock Generator /
Divider / Fan-Out Buffer
Multi−Level Inputs w/ Internal Termination
Description
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MARKING
DIAGRAM
1
The NB4L339 is a multi−function Clock generator featuring a 2:1
Clock multiplexer front end and simultaneously outputs a selection of
four different divide ratios from its four divider blocks;
÷1/÷2/÷4/÷8.
One divide block has a choice of
÷1
or
÷
2.
The output of each divider block is fanned−out to two identical
differential LVPECL copies of the selected clock. All outputs provide
standard LVPECL voltage levels when externally terminated with a
50−ohm resistor to V
CC
−
2 V.
The differential Clock inputs incorporate internal 50−W termination
resistors and will accept LVPECL, CML or LVDS logic levels.
The common Output Enable pin (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the internal clock
is in the LOW state. This avoids any chance of generating a runt clock
pulse on the internal clock when the device is enabled/disabled as can
happen with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal divider stages. The
internal enable flip−flop is clocked on the falling edge of the input
clock. Therefore, all associated specification limits are referenced to
the negative edge of the clock input.
This device is housed in a 5x5 mm 32 pin QFN package.
Features
1
32
QFN32
MN SUFFIX
CASE 488AM
NB4L339
AWLYYWWG
G
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Input/Output Clock Frequency > 700 MHz
Low Skew LVPECL Outputs, 15 ps typical
1 ns Typical Propagation Delay
150 ps Typical Rise and Fall Times
0.15 ps Typical RMS Phase Jitter
0.5 ps Typical RMS Random Clock Period Jitter
LVPECL, CML or LVDS Input Compatible
Operating Range: V
CC
= 2.375 V to 3.6 V with V
EE
= 0 V
LVPECL Output Level; 750 mV Peak−to−Peak, Typical
Internal 50−W Input Termination Provided
Synchronous Output Enable/Disable
Asynchronous Master Reset
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
•
−40°C
to 85°C Ambient Operating Temperature
•
32−Pin QFN, 5 mm x 5 mm
•
This is a Pb−Free Device
Figure 1. Simplified Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2012
1
September, 2012
−
Rev. 3
Publication Order Number:
NB4L339/D
NB4L339
DIVSEL
A
÷1
/
÷2
R
B
÷2
R
A
QA0
QA0
QA1
QA1
QB0
QB0
QB1
QB1
foutA = 622.08 MHz
or 311.04 MHz
CLKSEL
CLKA
VTA
CLKA
CLKB
VTB
CLKB
EN
50−W
50−W
B
foutB = 311.04 MHz
EXAMPLE: fin = 622.08 MHz
50−W
50−W
EN
C
÷4
R
C
QC0
QC0 foutC = 155.52 MHz
QC1
QC1
QD0
QD0
QD1
QD1
D
÷8
R
D
foutD = 77.76 MHz
MR
Figure 2. Detailed Logic Diagram
Table 1. Input Select Function Table
CLKSEL*
0
1
CLK Input Selected
CLKA
CLKB
Table 2. Divider Select Function Table
DIVSEL*
0
1
QA Divide
Divide by 1
Divide by 2
Table 3. Clock Enable/Disable Function Table
CLK Input
Low to High Transition
High to Low Transition
X (Don’t Care)
* Pin will default LOW when left OPEN.
EN*
0
1
X (Don’t Care)
MR**
H
H
L
Function
Divide
−
Outputs Active
Hold Q
−
Outputs Inactive
Reset Q
** Pin will default HIGH when left OPEN.
DIVSEL
QA0
QA0
QA1
QA1
V
CC
V
EE
CLKA
VTA
CLKA
CLKB
VTB
CLKB
V
EE
32 31
1
2
3
4
5
6
7
8
9
10
30 29 28 27
26 25
24
Exposed Pad (EP)
23
22
NB4L339
21
20
19
18
V
CC
MR
QB0
QB0
QB1
QB1
QC0
QC0
QC1
QC1
11
12 13 14
17
15 16
QD1
QD1
QD0
QD0
V
CC
EN
Figure 3. Pinout QFN−32 (Top View)
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2
CLKSEL
V
CC
NB4L339
Table 4. Pin Description
Pin
1, 8, EP
2
3
4
5
6
7
9, 16,
25, 32
10
11
12
13
14
15
17
18
19
20
21
22
23
24
26
27
28
29
30
31
−
Name
V
EE
CLKA
VTA
CLKA
CLKB
VTB
CLKB
V
CC
CLKSEL
QD1
QD1
QD0
QD0
EN
QC1
QC1
QC0
QC0
QB1
QB1
QB0
QB0
MR
QA1
QA1
QA0
QA0
DIVSEL
EP
I/O
−
LVPECL, CML,
LVDS Input
−
LVPECL, CML,
LVDS Input
LVPECL, CML,
LVDS Input
−
LVPECL, CML,
LVDS Input
−
LVCMOS/LVTTL
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVCMOS/LVTTL
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVCMOS/LVTTL
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVCMOS/LVTTL
−
Negative Supply Voltage
Non−inverted differential input (A). (Note 1)
Internal 100−W
center−tapped
termination pin for CLKA and CLKA (Note 1).
Inverted differential input (A). (Note 1)
Non−inverted differential input (B). (Note 1)
Internal 100−W
center−tapped
termination pin for CLKB and CLKB. (Note 1)
Inverted differential input (B). (Note 1)
Positive Supply Voltage
Asynchronous Clock input select pin. This pin defaults LOW when left open with 80 kW
resistor to V
EE
.
Inverted differential (D1) output. Typically terminated with 50
W
resistor to V
CC
– 2 V
Non−inverted Differential (D1) Output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Inverted differential (D0) output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Non−inverted Differential (D0) Output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Synchronous Output Enable/Disable pin. This pin defaults LOW when left open with 80 kW
resistor to V
EE
.
Inverted differential (C1) output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Non−inverted Differential (C1) Output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Inverted differential (C0) output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Non−inverted Differential (C0) Output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Inverted differential (B1) output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Non−inverted Differential (B1) Output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Inverted differential (B0) output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Non−inverted Differential (B0) Output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Master Reset Asynchronous. This pin defaults HIGH when left open with 80 kW resistor to
V
CC
.
Inverted differential (A1) output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Non−inverted Differential (A1) Output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Inverted differential (A0) output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Non−inverted Differential (A0) Output. Typically terminated with 50
W
resistor to V
CC
– 2 V.
Asynchronous Divide Select Pin selects A divide block outputs to divide by 1 or divide by 2.
Defaults LOW when left open, divide−by−1, with 80 kW resistor to V
EE
.
Exposed Pad. The exposed pad (EP) on package bottom (see case drawing) is thermally
connected to the die for improved heat transfer out of package and must be attached to a
heat−sinking conduit. The pad is electrically connected to V
EE
and must be connected to
V
EE
on the PC board.
Description
1. In the differential configuration when the input termination pin (VTx / VTx) are connected to a common termination voltage or left open, and
if no signal is applied on CLKx / CLKx input then the device will be susceptible to self−oscillation.
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NB4L339
Table 5. ATTRIBUTES
Characteristics
Input Default State Resistors
ESD Protection
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
QFN−32
Oxygen Index: 28 to 34
Value
80 kW
> 2.0 kV
> 100 V
Level 1
UL 94 V−0 @ 0.125 in
366
Table 6. MAXIMUM RATINGS
Symbol
V
CC
V
IO
V
INPP
I
IN
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Input/Output Voltage
Differential Input Voltage Swing
|CLK
−
CLK|
Static
Surge
Continuous
Surge
QFN−32
Condition 1
V
EE
= 0 V
V
EE
= 0 V
−0.5
= V
Io
≤
V
CC
+ 0.5
Condition 2
Rating
4.0
4.0
2.8
45
80
50
100
−40
to +85
−65
to +150
0 LFPM
500 LFPM
(Note 3)
QFN−32
QFN−32
QFN−32
31
27
12
265
Units
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C
Input Current Through R
T
(50
W
Resistor)
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder (Pb−Free)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB4L339
Table 7. DC CHARACTERISTICS, CLOCK Inputs, LVPECL Outputs
V
CC
= 2.375 V to 3.6 V, V
EE
= 0 V, T
A
=
−40°C
to +85°C (Note 5)
Symbol
I
EE
V
OH
Characteristic
Power Supply Current (Inputs and Outputs Open)
Min
58
Typ
70
Max
90
Unit
mA
LVPECL Outputs
(Note 4)
Output HIGH Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
V
OL
Output LOW Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
Differential Input Driven Single−Ended
(see Figures 6 & 8)
Vth
V
IH
V
IL
V
ISE
V
IHD
V
ILD
V
CMR
V
ID
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
Input Threshold Reference Voltage Range (Note 6)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Single−ended Input Voltage (V
IH
−
V
IL
)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration) (Note 8)
Differential Input Voltage Swing (V
IHD
−
V
ILD
)
Input HIGH Current
Input LOW Current
CLKx / CLKx
CLKx / CLKx
(VTx Open)
(VTx Open)
1125
Vth + 75
V
EE
150
V
CC
−
75
V
CC
Vth
−
75
2800
mV
mV
mV
mV
V
CC
−
1135
2155
1355
V
CC
−
1935
1355
555
V
CC
−
1020
2280
1480
V
CC
−
1770
1530
730
V
CC
−
760
2540
1740
V
CC
−
1560
1740
940
mV
mV
Differential Inputs Driven Differentially
(see Figures 7 & 9)
1200
V
EE
1125
150
10
−10
V
CC
V
CC
−
150
V
CC
−
75
2800
40
10
mV
mV
mV
mV
mA
mA
Single−Ended LVCMOS / LVTTL Control Inputs
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input HIGH Current
Input LOW Current
CLKSEL, DIVSEL, EN
MR
CLKSEL, DIVSEL, EN
MR
2000
V
EE
40
−10
−10
−115
V
CC
800
115
10
10
−40
mV
mV
mA
mA
Termination Resistors
R
TIN
R
TIN
Internal Input Termination Resistor (Measured across CLKx and CLKx)
Internal Input Termination Resistor (Measured from CLKx to VTx)
80
40
100
50
120
60
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL outputs require 50
W
receiver termination resistors to V
CC
−
2 V for proper operation.
5. Input and output parameters vary 1:1 with V
CC
.
6. Vth is applied to the complementary input when operating in single−ended mode.
7. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
8. V
CMR
min varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential input
signal.
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