Data Communications ICs
High-Level Serial Communication
Controller Extended (HSCX)
SAB 82525; SAB 82526
SAF 82525; SAF 82526
User’s Manual 10.94
SAB 82525; SAF 82525; SAB 82526; SAF 82526
Revision History:
10.94
Previous Releases:
Page
01.92
Subjects (changes since last revision)
Update
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause irrevers-
ible damage to the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specify mean values expected over the production spread. If not otherwise
specified, typical characteristics apply at
T
A
= 25
°C
and the given supply voltage.
Operating Range
In the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about “Processing
Guidelines”
and
“Quality
Assurance”
for ICs, see our “Product
Overview”.
Edition 10.94
This edition was realized using the software system FrameMaker
®
.
Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation,
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Siemens AG 1994. All Rights Reserved.
As far as patents or other rights of third parties are concerned, liability is only assumed for components , not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery, and prices please contact the Offices of Semiconductor Group in Germany
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General Information
Table of Contents
Page
1
Features
..................................................................................................................... 6
1.1
Pin Definitions and Functions ................................................................................... 10
1.2
System Integration .................................................................................................... 17
1.3
Functional Description .............................................................................................. 22
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3
3.1
3.2
3.3
4
4.1
4.2
4.3
4.4
4.5
5
5.1
5.2
5.3
5.4
5.5
6
6.1
6.2
6.3
6.4
6.5
6.6
Operating Modes
..................................................................................................... 24
Auto-Mode (MODE: MDS1, MDS0 = 00) .................................................................. 24
Non-Auto Mode (MODE: MDS1, MDS0 = 01) .......................................................... 24
Transparent Mode 1 (MODE: MDS1, MDS0, ADM = 101) ....................................... 25
Transparent Mode 0 (MODE: MDS1, MDS0, ADM = 100) ....................................... 25
Extended Transparent Modes 0; 1 (MODE: MDS1, MDS0 = 11) ............................. 25
Receive Data Flow (Summary) ................................................................................. 26
Transmit Data Flow ................................................................................................... 27
Procedural Support (Layer-2 Functions)
.............................................................. 28
Full-Duplex LAPB/LAPD Operation .......................................................................... 28
Half-Duplex SDLC-NRM Operation .......................................................................... 34
Error Handling ........................................................................................................... 38
CPU Interface
.......................................................................................................... 38
Register Set .............................................................................................................. 38
Data Transfer Modes ................................................................................................. 38
Interrupt Interface ...................................................................................................... 39
DMA Interface ........................................................................................................... 43
FIFO Structure .......................................................................................................... 47
Serial Interface (Layer-1 Functions)
...................................................................... 49
Clock Modes .............................................................................................................. 49
Clock Recovery (DPLL) ............................................................................................ 57
Bus Configuration ..................................................................................................... 60
Data Encoding .......................................................................................................... 63
Modem Control Functions (RTS/CTS, CD) ............................................................... 63
Special Functions
................................................................................................... 65
Fully Transparent Transmission and Reception ....................................................... 65
Cyclic Transmission (Fully Transparent) ................................................................... 65
Continuous Transmission (DMA Mode only) ............................................................ 66
Receive Length Check Feature ................................................................................ 66
One Bit Insertion ....................................................................................................... 67
Data Inversion........................................................................................................... 67
Semiconductor Group
3
General Information
Table of Contents
Page
6.8
Test Mode ................................................................................................................. 68
6.7
Special RTS Function ............................................................................................... 68
7
7.1
7.2
7.3
7.4
7.5
8
8.1
8.2
9
10
11
Operational Description
......................................................................................... 69
RESET ...................................................................................................................... 69
Initialization ............................................................................................................... 70
Operational Phase .................................................................................................... 71
Data Transmission .................................................................................................... 71
Data Reception ......................................................................................................... 75
Detailed Register Description................................................................................
79
Register Address Arrangement ................................................................................. 79
Register Definitions ................................................................................................... 80
Electrical Characteristics
..................................................................................... 108
Quartz Specifications
........................................................................................... 118
Package Outlines
.................................................................................................. 125
Semiconductor Group
4
General Information
The SAB 82525 is a High-Level Serial Communication Controller compatible to the SAB 82520
HSCC with extended features and functionality (HSCX).
The SAB 82526 is pin and software compatible to the SAB 82525, realizing one HDLC channel
(channel B).
The HSCX has been designed to implement high-speed communication links using HDLC
protocols and to reduce the hardware and software overhead needed for serial synchronous
communications.
Due to its 8-bit demultiplexed adaptive bus interface it fits perfectly into every Siemens/Intel or
Motorola 8- or 16-bit microcontroller or microprocessor system. The data through-put from/to
system memory is optimized transferring blocks of data (usually 32 bytes) by means of DMA
or interrupt request. Together with the storing capacity of up to 64 bytes in on-chip FIFO’s, the
serial interfaces are effectively decoupled from the system bus which drastically reduces the
dynamic load and reaction time of the CPU.
The HSCX directly supports the X.25 LAPB, the ISDN LAPD, and SDLC (normal response
mode) protocols and is capable of handling a large set of layer-2 protocol functions
independently from the host processor.
Furthermore, the HSCX opens a wide area for applications which use time division multiplex
methods (e.g. time-slot oriented PCM systems, systems designed for packet switching, ISDN
applications) by its programmable telecom-specific features.
The HSCX is fabricated using Siemens advanced ACMOS 3 technology and available in a
P-LCC-44 pin package.
The data link controller handles all functions necessary to establish and maintain an HDLC
data link, such as
– Flag insertion and detection,
– Bit stuffing,
– CRC generation and checking,
– Address field recognition.
Associated with each serial channel is a set of independent command and status registers
(SP-REG) and 64-byte deep FIFO’s for transmit and receive direction.
DMA capability has been added to the HSCX by means of a 4-channel DMA interface
(SAB 82525) with one DMA request line for each transmitter and receiver of both channels.
General
Advanced CMOS technology
Low power consumption: active 25 mW at 4 MHz
standby 4 mW
Semiconductor Group
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